# US 12,224,329 B2 · Trench transistor

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- Number: US 12,224,329 B2
- Document ID: US12224329B2
- Status: Granted
- Kind: B2
- Application number: 17/635,823
- Filed: 2020-08-24
- Published: 2022-10-06
- Granted: 2025-02-11
- Earliest claimed: 2019-08-23
- Assignees: Robert Bosch GmbH
- Applicants: Robert Bosch GmbH
- Inventors: Christian Tobias Banzhaf; Jan-Hendrik Alsmeier; Stephan Schwaiger; Wolfgang Feiler; Dick Scholten; Klaus Heyers
- Web page: https://patentgrep.com/patent/US12224329B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 30/665: {having edge termination structures}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/8325: {Silicon carbide}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A trench transistor. The transistor including: a semiconductor region, a trench structure formed in the semiconductor region; a gate insulation layer and an electrically conductive gate layer formed on the gate insulation layer in the trench structure, and a gate contact, which is electrically conductively connected to the gate layer in an edge area of the trench transistor. A thickness of the gate insulation layer in the edge area of the trench transistor is greater than in an active area of the trench transistor.

## Claims

### Claim 1

A trench transistor, comprising:
a semiconductor region;
a trench structure formed in the semiconductor region;
a gate insulation layer and an electrically conductive gate layer formed on the gate insulation layer in the trench structure; and
a gate contact, which is electrically conductively connected to the electrically conductive gate layer in an edge area of the trench transistor, a thickness of the gate insulation layer in the edge area of the trench transistor being greater than a thickness in an active area of the trench transistor,
wherein a width of the trench structure increases continuously from the active area of the trench transistor to the edge area of the trench transistor.

### Claim 2 (depends on 1)

The trench transistor as recited in claim 1, wherein the electrically conductive gate layer in the edge area of the trench transistor extends out of the trench structure over the semiconductor region.

### Claim 3 (depends on 2)

The trench structure as recited in claim 2, further comprising:
a second trench structure and a second gate insulation layer in the second trench structure;
wherein the electrically conductive gate layer is furthermore formed on the second gate insulation layer in the second trench structure, and a thickness of the second gate insulation layer in the edge area of the trench transistor is greater than the thickness in the active area of the trench transistor.

### Claim 4

A trench transistor, comprising:
a semiconductor region;
a first trench structure and a second trench structure in the semiconductor region;
a trench connecting structure in the semiconductor region, which connects an edge area of the first trench structure and an edge area of the second trench structure to one another;
a third trench structure in the semiconductor region, which is connected to the trench connecting structure;
a gate insulation layer in the trench structures and the trench connecting structure;
an electrically conductive gate layer in the first, second, and third trench structures and the trench connecting structure; and
a gate contact, which is electrically conductively connected to the electrically conductive gate layer in the third trench structure, at least at an edge area of the third trench structure, a width of the third trench structure being greater than a width of the first trench structure and/or a width of the second trench structure,
wherein the third trench structure includes a first area and a second area, a width of the first area increasing toward the second area up to a width of the second area.

### Claim 5 (depends on 4)

The trench transistor as recited in claim 4, further comprising:
an insulation layer above the semiconductor region; and
an electrical through-contact through the insulation layer, which is connected to the electrically conductive gate layer in the third trench structure.

### Claim 6 (depends on 4)

The trench transistor as recited in claim 4, wherein at the edge area of the third trench structure, a radius of curvature of the third trench structure is greater than a radius of curvature of the first trench structure at an edge area of the first trench structure and/or than a radius of curvature of the second trench structure at an edge region of the second trench structure.

### Claim 7 (depends on 4)

The trench transistor as recited in claim 4, wherein the third trench structure is situated on a center line between the first trench structure and the second trench structure in an edge area of the trench transistor.

### Claim 8 (depends on 4)

The trench transistor as recited in claim 4, wherein the third trench structure is formed in parallel to the first trench structure and the second trench structure and extends in extension of the first trench structure or the second trench structure in an edge area of the trench transistor.

### Claim 9 (depends on 8)

The trench transistor as recited in claim 8, wherein the electrically conductive gate layer completely fills the third trench structure and extends out of the third trench structure over the semiconductor region.

### Claim 10

A trench transistor, comprising:
a semiconductor region;
a plurality of trench structures situated adjacent to one another in the semiconductor region;
a trough in the semiconductor region connected in an edge area of the trench transistor to the plurality of trench structures;
a gate insulation layer and an electrically conductive gate layer formed on the gate insulation layer in the trench structures and in the trough; and
a gate contact, which is electrically conductively connected to the electrically conductive gate layer in the trough, the trough extending at least from a first outermost trench structure of the plurality of trench structures laterally up to a second outermost trench structure of the plurality of trench structures, which is farthest away from the first outermost trench structure,
wherein the width of the trench structure increases continuously from the active area of the trench transistor to the edge area of the trench transistor.

### Claim 11

A trench transistor, comprising:
a semiconductor region;
a trench structure formed in the semiconductor region;
a gate insulation layer and an electrically conductive gate layer formed on the gate insulation layer in the trench structure; and
a gate contact, which is electrically conductively connected to the electrically conductive gate layer in an edge area of the trench transistor, a width of the trench structure being greater in the edge area of the trench transistor than in an active area of the trench transistor,
wherein the width of the trench structure increases continuously from the active area of the trench transistor to the edge area of the trench transistor.