# US 12,224,328 B2 · Semiconductor device having word line structure

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- Number: US 12,224,328 B2
- Document ID: US12224328B2
- Status: Granted
- Kind: B2
- Application number: 17/699,331
- Filed: 2022-03-21
- Published: 2023-09-21
- Granted: 2025-02-11
- Earliest claimed: 2022-03-21
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Cheng-Yan Ji; Wei-Tong Chen
- Web page: https://patentgrep.com/patent/US12224328B2

## CPC

- H10D 64/027: {by etching at gate locations}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/488: {Word lines}
- H10D 64/01: Manufacture or treatment
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a word line structure. The semiconductor substrate has an active region. The word line structure is disposed in the active region of the semiconductor substrate. The word line structure includes a first work function layer, a second work function layer, and a buffer structure. The second work function layer is on the first work function layer. The buffer structure is between the first work function layer and the second work function layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate having an active region; and
a word line structure disposed in the active region of the semiconductor substrate, the word line structure comprising:
a first work function layer;
a second work function layer on the first work function layer;
a buffer structure having a bottom buffer layer between the first work function layer and the second work function layer; and
a barrier layer having a top portion between the bottom buffer layer of the buffer structure and the first work function layer;
wherein the word line structure further comprises:
a dielectric layer surrounding the buffer structure, the barrier layer, the first work function layer and the second work function layer, wherein the buffer structure and the dielectric layer comprise a same material.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the bottom buffer layer of the buffer structure directly contacts the second work function layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the buffer structure surrounds a plurality of surfaces of the second work function layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the buffer structure comprises:
a top buffer layer on the second work function layer; and
two side buffer layers integrally extended between the bottom buffer layer and the top buffer layer to surround the second work function layer.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the buffer structure directly contacts a top surface, a bottom surface, and a plurality of lateral surfaces of the second work function layer via the top buffer layer, the bottom buffer layer, and the side buffer layers respectively.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the barrier layer further has a bottom portion extended from the top portion to surround the first work function layer.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the top portion of the barrier layer directly contacts with the bottom buffer layer of the buffer structure and the first work function layer, wherein the bottom portion of the barrier layer directly contacts with a bottom surface of the first work function layer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the buffer structure has a thickness from about 1 nm to about 2 nm.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first work function layer comprises metal, and the second work function layer comprises doped polysilicon.

### Claim 10

A semiconductor device, comprising:
a semiconductor substrate having a trench;
a word line structure disposed in the trench of the semiconductor substrate, the word line structure comprising:
a doped-polysilicon layer;
a buffer structure having a bottom buffer layer directly contacting a bottom surface of the doped-polysilicon layer;
a barrier layer having a top portion directly contacting with the bottom buffer layer of the buffer structure; and
a dielectric structure in the trench and over the doped-polysilicon layer;
wherein the buffer structure further comprises a top portion directly contacting a top surface of the doped-polysilicon layer.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the word line structure further comprises:
a conductive layer, wherein the bottom buffer layer of the buffer structure is between the conductive layer and the bottom surface of the doped-polysilicon layer, wherein the top portion of the barrier layer is in direct contact with the conductive layer.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the word line structure further comprises a dielectric layer on an inner sidewall of the trench, wherein the buffer structure directly contacts the dielectric layer, wherein the buffer structure, the barrier layer, the conductive layer, and the doped-polysilicon layer are surrounded by the dielectric layer.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the buffer structure and the dielectric layer comprise an oxide material.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein the dielectric structure comprises a bottom portion directly contacting the top portion of the buffer structure and an upper portion above a top surface of the semiconductor substrate.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the word line structure further comprises:
an overlaying layer disposed between the upper portion of the dielectric structure and the top surface of the semiconductor substrate.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the overlaying layer has an opening exposing the trench of the semiconductor substrate.

### Claim 17 (depends on 10)

The semiconductor device of claim 10, wherein the buffer structure has a thickness from about 1 nm to about 2 nm.