# US 12,224,327 B2 · Semiconductor device and method

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- Number: US 12,224,327 B2
- Document ID: US12224327B2
- Status: Granted
- Kind: B2
- Application number: 18/366,369
- Filed: 2023-08-07
- Published: 2023-12-21
- Granted: 2025-02-11
- Earliest claimed: 2020-09-23
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Kuo-Ju Chen; Shih-Hsiang Chiu; Su-Hao Liu; Liang-Yin Chen; Huicheng Chang; Yee-Chia Yeo
- Web page: https://patentgrep.com/patent/US12224327B2

## CPC

- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 64/01: Manufacture or treatment
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10P 14/418: {the conductive layers comprising transition metals}
- H10P 30/40: into insulating materials
- H10P 32/30: Diffusion for doping of conductive or resistive layers
- H10P 50/283: {by chemical means}
- H10W 20/051: {by ion implantation}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/095: {by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096)}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10W 20/034: {bottomless barrier, adhesion or liner layers}
- H10W 20/076: {in via holes or trenches}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

## Claims

### Claim 1

A semiconductor device, comprising:
a first dielectric layer over a conductive feature, wherein a first portion of the first dielectric layer comprises a first dopant;
a metal feature electrically coupled to the conductive feature, the metal feature comprising:
a first contact material in contact with the conductive feature;
a second contact material over the first contact material, the second contact material comprising a material different from the first contact material, wherein a first portion of the second contact material further comprises the first dopant; and
a dielectric liner between the first dielectric layer and the metal feature, wherein a first portion of the dielectric liner comprises the first dopant.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first dopant comprises germanium.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first contact material comprises cobalt (Co) and the second contact material comprises tungsten.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first portion of the first dielectric layer, the first portion of the second contact material, and the first portion of the dielectric liner each extend to depths ranging from 1 nm to 15 nm.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein top surfaces of the first dielectric layer, the metal feature, and the dielectric liner are level with one another.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a second dielectric layer over the conductive feature, wherein a first portion of the second dielectric layer is doped with the first dopant, wherein the first dielectric layer and the second dielectric layer each contact sidewalls of the dielectric liner, and wherein the first dielectric layer and the second dielectric layer each comprise different materials.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the first dielectric layer comprises silicon oxide and the second dielectric layer comprises silicon nitride.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein a maximum concentration of the first dopant in each of the first portion of the first dielectric layer, the first portion of the second contact material, and the first portion of the dielectric liner is at a top surface of the first portion of the first dielectric layer, the first portion of the second contact material, and the first portion of the dielectric liner, respectively.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein a maximum concentration of the first dopant in each of the first portion of the first dielectric layer, the first portion of the second contact material, and the first portion of the first dielectric layer is below a top surface of the first portion of the first dielectric layer, the first portion of the second contact material, and the first portion of the first dielectric layer, respectively.

### Claim 10

A semiconductor device comprising:
a first dielectric layer over a substrate and a conductive feature;
a first doped dielectric layer over the first dielectric layer;
a first metal portion;
a second metal portion in the first dielectric layer and electrically coupled to the conductive feature, wherein the first metal portion is between the second metal portion and the conductive feature, the first metal portion electrically coupling the second metal portion to the conductive feature, the second metal portion comprising a different metal than the first metal portion;
a doped metal portion over the second metal portion, wherein the second metal portion and the doped metal portion comprise a same metal material;
a dielectric liner between the first dielectric layer and the second metal portion; and
a doped liner over the dielectric liner and between the first doped dielectric layer and the doped metal portion, wherein the first doped dielectric layer, the doped liner, and the doped metal portion each comprise first dopants.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the first dopants comprise xenon.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the first metal portion comprises cobalt.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein the dielectric liner contacts sidewalls of the first metal portion and the second metal portion, and wherein the doped liner contacts sidewalls of the second metal portion.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein bottom extents of the first doped dielectric layer, the doped metal portion, and the doped liner are aligned with one another.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, wherein a thickness of the second metal portion is non-uniform.

### Claim 16

A semiconductor device, comprising:
a first dielectric layer over a conductive feature; and
a contact structure extending through the first dielectric layer to the conductive feature, the contact structure comprising:
a dielectric liner adjacent sidewalls of the first dielectric layer, the dielectric liner comprising a doped liner portion and an undoped liner portion;
a first metal portion over the conductive feature, the dielectric liner being between the first dielectric layer and the first metal portion; and
a second metal portion over the first metal portion, the second metal portion comprising a material different from the first metal portion, the second metal portion comprises a doped second metal portion and an undoped second metal portion, the doped second metal portion comprising a first dopant, the undoped second metal portion being between the doped second metal portion and the first metal portion, the dielectric liner being between the first dielectric layer and the second metal portion.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein a thickness of the doped second metal portion is in a range between 1 nm and 15 nm.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein the first dopant comprises germanium.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, further comprising a second dielectric layer over the conductive feature, wherein a first portion of the second dielectric layer is doped with the first dopant, wherein the first dielectric layer and the second dielectric layer each contact sidewalls of the dielectric liner.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein a bottom of the doped liner portion is above a top of the first metal portion.