# US 12,224,326 B2 · Contact architecture for capacitance reduction and satisfactory contact resistance > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,326 B2 - Document ID: US12224326B2 - Status: Granted - Kind: B2 - Application number: 18/378,472 - Filed: 2023-10-10 - Published: 2024-02-01 - Granted: 2025-02-11 - Earliest claimed: 2020-10-30 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Rishabh Mehandru; Pratik A. Patel; Ralph T. Troeger; Szuya S. Liao - Web page: https://patentgrep.com/patent/US12224326B2 ## CPC - H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts} - H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs} - H10D 30/0212: {using self-aligned silicidation} - H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 64/01: Manufacture or treatment - H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers} - H10D 64/62: Electrodes ohmically coupled to a semiconductor - H10D 64/679: {comprising air gaps} - H10P 14/24: using chemical vapour deposition [CVD] - H10P 14/3442: {N-type} - H10P 14/3444: {P-type} - H10P 30/204: {into Group IV semiconductors} - H10P 30/21: {of electrically active species} - H10P 30/28: characterised by an annealing step, e.g. for activation of dopants - H10P 50/642: {Chemical etching} - H10P 95/04: {Planarisation of conductive or resistive materials} - H10W 20/076: {in via holes or trenches} - H10W 20/083: {the openings being via holes penetrating underlying conductors} - H10D 64/0112: {using conductive layers comprising silicides} - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween. ## Claims ### Claim 1 An integrated circuit structure, comprising: a fin comprising silicon; a first epitaxial source or drain region and a second epitaxial source or drain region in the fin; a first contact member on the first epitaxial source or drain region, and a second contact member on the second epitaxial source or drain region; a first conductive interconnect on the first contact member, the first conductive interconnect having an uppermost surface; a first dielectric layer adjacent to the first conductive interconnect, the first dielectric layer having an uppermost surface at a same level as the uppermost surface of the first conductive interconnect, the first dielectric layer in contact with the first epitaxial source or drain region, and the first dielectric layer having a first composition; a second dielectric layer having a vertical interface with the first dielectric layer, the second dielectric layer having an uppermost surface at a same level as the uppermost surface of the first dielectric layer, and the second dielectric layer having a second composition different than the first composition; a gate contact over the fin, the gate contact having a first side and a second side opposite the first side, wherein the second dielectric layer is between the first side of the gate contact and the first dielectric layer, the gate contact having an uppermost surface at a same level as the uppermost surface of the second dielectric layer; a third dielectric layer adjacent to the second side of the gate contact, the third dielectric layer having an uppermost surface at a same level as the uppermost surface of the gate contact, and the third dielectric layer having the second composition; a fourth dielectric layer having a vertical interface with the third dielectric layer, the fourth dielectric layer having an uppermost surface at a same level as the uppermost surface of the third dielectric layer, and the fourth dielectric layer having the first composition; and a second conductive interconnect on the second contact member, the second conductive interconnect adjacent to the fourth dielectric layer, and the second conductive interconnect having an uppermost surface at a same level as the uppermost surface of the fourth dielectric layer. ### Claim 2 (depends on 1) The integrated circuit structure of claim 1, wherein each of the first contact member and the second contact member comprises a metal selected from the group consisting of copper, aluminum, tungsten, titanium, tantalum, silver, gold, palladium, platinum, zinc, and nickel. ### Claim 3 (depends on 1) The integrated circuit structure of claim 1, wherein each of the first conductive interconnect and the second conductive interconnect comprises a metal selected from the group consisting of copper, aluminum, tungsten, titanium, tantalum, silver, gold, palladium, platinum, zinc, and nickel. ### Claim 4 (depends on 1) The integrated circuit structure of claim 1, further comprising: a gate dielectric between the gate contact and the fin. ### Claim 5 (depends on 4) The integrated circuit structure of claim 4, wherein the gate dielectric comprises a high-k material. ### Claim 6 (depends on 1) The integrated circuit structure of claim 1, wherein the first and second epitaxial source or drain region are p-type source or drain regions. ### Claim 7 (depends on 1) The integrated circuit structure of claim 1, wherein the first and second epitaxial source or drain region are n-type source or drain regions. ### Claim 8 (depends on 1) The integrated circuit structure of claim 1, wherein each of the first contact member and the second contact member has a top surface at a same level as a top of the fin. ### Claim 9 (depends on 1) The integrated circuit structure of claim 1, wherein each of the first contact member and the second contact member has a curved bottom surface. ### Claim 10 (depends on 1) The integrated circuit structure of claim 1, wherein the first epitaxial source or drain region has an interface with the fin laterally between the first conductive interconnect and the vertical interface of the first and second dielectric layers, and wherein the second epitaxial source or drain region has an interface with the fin laterally between the second conductive interconnect and the vertical interface of the third and fourth dielectric layers. ### Claim 11 (depends on 1) The integrated circuit structure of claim 1, wherein the fourth dielectric layer is in contact with the second epitaxial source or drain region. ### Claim 12 An integrated circuit structure, comprising: a nanowire; a first epitaxial source or drain region and a second epitaxial source or drain region in the nanowire; a first contact member on the first epitaxial source or drain region, and a second contact member on the second epitaxial source or drain region; a first conductive interconnect on the first contact member, the first conductive interconnect having an uppermost surface; a first dielectric layer adjacent to the first conductive interconnect, the first dielectric layer having an uppermost surface at a same level as the uppermost surface of the first conductive interconnect, the first dielectric layer in contact with the first epitaxial source or drain region, and the first dielectric layer having a first composition; a second dielectric layer having a vertical interface with the first dielectric layer, the second dielectric layer having an uppermost surface at a same level as the uppermost surface of the first dielectric layer, and the second dielectric layer having a second composition different than the first composition; a gate contact over the nanowire, the gate contact having a first side and a second side opposite the first side, wherein the second dielectric layer is between the first side of the gate contact and the first dielectric layer, the gate contact having an uppermost surface at a same level as the uppermost surface of the second dielectric layer; a third dielectric layer adjacent to the second side of the gate contact, the third dielectric layer having an uppermost surface at a same level as the uppermost surface of the gate contact, and the third dielectric layer having the second composition; a fourth dielectric layer having a vertical interface with the third dielectric layer, the fourth dielectric layer having an uppermost surface at a same level as the uppermost surface of the third dielectric layer, and the fourth dielectric layer having the first composition; and a second conductive interconnect on the second contact member, the second conductive interconnect adjacent to the fourth dielectric layer, and the second conductive interconnect having an uppermost surface at a same level as the uppermost surface of the fourth dielectric layer. ### Claim 13 (depends on 12) The integrated circuit structure of claim 12, wherein each of the first contact member and the second contact member comprises a metal selected from the group consisting of copper, aluminum, tungsten, titanium, tantalum, silver, gold, palladium, platinum, zinc, and nickel. ### Claim 14 (depends on 12) The integrated circuit structure of claim 12, wherein each of the first conductive interconnect and the second conductive interconnect comprises a metal selected from the group consisting of copper, aluminum, tungsten, titanium, tantalum, silver, gold, palladium, platinum, zinc, and nickel. ### Claim 15 (depends on 12) The integrated circuit structure of claim 12, further comprising: a gate dielectric between the gate contact and the nanowire. ### Claim 16 (depends on 15) The integrated circuit structure of claim 15, wherein the gate dielectric comprises a high-k material. ### Claim 17 (depends on 12) The integrated circuit structure of claim 12, wherein the first and second epitaxial source or drain region are p-type source or drain regions. ### Claim 18 (depends on 12) The integrated circuit structure of claim 12, wherein the first and second epitaxial source or drain region are n-type source or drain regions. ### Claim 19 (depends on 12) The integrated circuit structure of claim 12, wherein each of the first contact member and the second contact member has a top surface at a same level as a top of the nanowire. ### Claim 20 (depends on 12) The integrated circuit structure of claim 12, wherein each of the first contact member and the second contact member has a curved bottom surface. ### Claim 21 (depends on 12) The integrated circuit structure of claim 12, wherein the first epitaxial source or drain region has an interface with the nanowire laterally between the first conductive interconnect and the vertical interface of the first and second dielectric layers, and wherein the second epitaxial source or drain region has an interface with the nanowire laterally between the second conductive interconnect and the vertical interface of the third and fourth dielectric layers. ### Claim 22 An integrated circuit structure, comprising: a fin comprising silicon; a first epitaxial source or drain region and a second epitaxial source or drain region in the fin; a first contact member on the first epitaxial source or drain region, and a second contact member on the second epitaxial source or drain region; a first conductive interconnect on the first contact member, the first conductive interconnect having an uppermost surface; a first dielectric layer adjacent to the first conductive interconnect, the first dielectric layer having an uppermost surface at a same level as the uppermost surface of the first conductive interconnect, and the first dielectric layer having a first composition; a second dielectric layer having a vertical interface with the first dielectric layer, the second dielectric layer having an uppermost surface at a same level as the uppermost surface of the first dielectric layer, and the second dielectric layer having a second composition different than the first composition; a gate contact over the fin, the gate contact having a first side and a second side opposite the first side, wherein the second dielectric layer is between the first side of the gate contact and the first dielectric layer, the gate contact having an uppermost surface at a same level as the uppermost surface of the second dielectric layer; a third dielectric layer adjacent to the second side of the gate contact, the third dielectric layer having an uppermost surface at a same level as the uppermost surface of the gate contact, and the third dielectric layer having the second composition; a fourth dielectric layer having a vertical interface with the third dielectric layer, the fourth dielectric layer having an uppermost surface at a same level as the uppermost surface of the third dielectric layer, and the fourth dielectric layer having the first composition; and a second conductive interconnect on the second contact member, the second conductive interconnect adjacent to the fourth dielectric layer, and the second conductive interconnect having an uppermost surface at a same level as the uppermost surface of the fourth dielectric layer, wherein each of the first contact member and the second contact member has a top surface at a same level as a top of the fin. ### Claim 23 An integrated circuit structure, comprising: a fin comprising silicon; a first epitaxial source or drain region and a second epitaxial source or drain region in the fin; a first contact member on the first epitaxial source or drain region, and a second contact member on the second epitaxial source or drain region; a first conductive interconnect on the first contact member, the first conductive interconnect having an uppermost surface; a first dielectric layer adjacent to the first conductive interconnect, the first dielectric layer having an uppermost surface at a same level as the uppermost surface of the first conductive interconnect, and the first dielectric layer having a first composition; a second dielectric layer having a vertical interface with the first dielectric layer, the second dielectric layer having an uppermost surface at a same level as the uppermost surface of the first dielectric layer, and the second dielectric layer having a second composition different than the first composition; a gate contact over the fin, the gate contact having a first side and a second side opposite the first side, wherein the second dielectric layer is between the first side of the gate contact and the first dielectric layer, the gate contact having an uppermost surface at a same level as the uppermost surface of the second dielectric layer; a third dielectric layer adjacent to the second side of the gate contact, the third dielectric layer having an uppermost surface at a same level as the uppermost surface of the gate contact, and the third dielectric layer having the second composition; a fourth dielectric layer having a vertical interface with the third dielectric layer, the fourth dielectric layer having an uppermost surface at a same level as the uppermost surface of the third dielectric layer, and the fourth dielectric layer having the first composition; and a second conductive interconnect on the second contact member, the second conductive interconnect adjacent to the fourth dielectric layer, and the second conductive interconnect having an uppermost surface at a same level as the uppermost surface of the fourth dielectric layer, wherein each of the first contact member and the second contact member has a curved bottom surface. ### Claim 24 An integrated circuit structure, comprising: a fin comprising silicon; a first epitaxial source or drain region and a second epitaxial source or drain region in the fin; a first contact member on the first epitaxial source or drain region, and a second contact member on the second epitaxial source or drain region; a first conductive interconnect on the first contact member, the first conductive interconnect having an uppermost surface; a first dielectric layer adjacent to the first conductive interconnect, the first dielectric layer having an uppermost surface at a same level as the uppermost surface of the first conductive interconnect, and the first dielectric layer having a first composition; a second dielectric layer having a vertical interface with the first dielectric layer, the second dielectric layer having an uppermost surface at a same level as the uppermost surface of the first dielectric layer, and the second dielectric layer having a second composition different than the first composition; a gate contact over the fin, the gate contact having a first side and a second side opposite the first side, wherein the second dielectric layer is between the first side of the gate contact and the first dielectric layer, the gate contact having an uppermost surface at a same level as the uppermost surface of the second dielectric layer; a third dielectric layer adjacent to the second side of the gate contact, the third dielectric layer having an uppermost surface at a same level as the uppermost surface of the gate contact, and the third dielectric layer having the second composition; a fourth dielectric layer having a vertical interface with the third dielectric layer, the fourth dielectric layer having an uppermost surface at a same level as the uppermost surface of the third dielectric layer, and the fourth dielectric layer having the first composition; and a second conductive interconnect on the second contact member, the second conductive interconnect adjacent to the fourth dielectric layer, and the second conductive interconnect having an uppermost surface at a same level as the uppermost surface of the fourth dielectric layer, wherein the first epitaxial source or drain region has an interface with the fin laterally between the first conductive interconnect and the vertical interface of the first and second dielectric layers, and wherein the second epitaxial source or drain region has an interface with the fin laterally between the second conductive interconnect and the vertical interface of the third and fourth dielectric layers.