# US 12,224,325 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 12,224,325 B2
- Document ID: US12224325B2
- Status: Granted
- Kind: B2
- Application number: 18/353,027
- Filed: 2023-07-14
- Published: 2024-01-18
- Granted: 2025-02-11
- Earliest claimed: 2019-08-21
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Li-Zhen Yu; Chia-Hao Chang; Cheng-Chi Chuang; Yu-Ming Lin; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US12224325B2

## CPC

- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 64/01: Manufacture or treatment
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10P 14/432: {using selective deposition}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 50/283: {by chemical means}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 50/268: {of silicon-containing layers}
- H10P 50/73: {using masks for insulating materials}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a gate structure over the substrate;
source/drain regions in the substrate and on opposite sides of the gate structure;
a source/drain contact over one of the source/drain regions;
a metal cap over the source/drain contact, wherein a bottom surface of the metal cap is higher than a top surface of the gate structure;
a contact plug over the metal cap; and
a first etch stop layer over the gate structure, wherein the first etch stop layer is in contact with the metal cap and the contact plug.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a second etch stop layer over the first etch stop layer; and
an interlayer dielectric layer over the second etch stop layer, wherein the second etch stop layer and the interlayer dielectric layer are in contact with a sidewall of the contact plug.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first etch stop layer and the second etch stop layer are made of different materials.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the contact plug is in contact with a top surface and a sidewall of the metal cap.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first etch stop layer is in contact with a sidewall and a bottom surface of the contact plug.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a gate spacer on a sidewall of the gate structure, wherein the gate spacer is in contact with the metal cap.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a top surface of the metal cap is substantially level with a topmost surface of the first etch stop layer.

### Claim 8

A semiconductor device, comprising:
a substrate;
a gate structure over the substrate;
source/drain regions in the substrate and on opposite sides of the gate structure;
a source/drain contact over one of the source/drain regions;
a metal cap over the source/drain contact;
a contact plug over the metal cap, wherein the contact plug is in contact with at least three sides of the metal cap in a cross-sectional view;
a first etch stop layer extending from a sidewall of the metal cap to a sidewall of the contact plug;
a second etch stop layer over the first etch stop layer; and
an interlayer dielectric layer over the second etch stop layer, wherein the second etch stop layer and the interlayer dielectric layer are in contact with the sidewall of the contact plug.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the first etch stop layer comprises a thicker portion and a narrower portion that is thinner than the thicker portion, wherein the narrower portion is vertically below the contact plug.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the contact plug is separated from the source/drain contact through the metal cap.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, further comprising a gate spacer on a sidewall of the gate structure, wherein the gate spacer is in contact with the metal cap.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, further comprising a protective layer over and in contact with a top surface of the gate structure, wherein the protective layer is in contact with the metal cap.

### Claim 13

A method, comprising:
forming a gate structure over a substrate;
forming source/drain regions over the substrate and on opposite sides of the gate structure;
forming a source/drain contact over one of the source/drain regions;
forming a protective cap over the gate structure;
forming a first etch stop layer over the protective cap;
forming a metal cap over the source/drain contact, wherein the metal cap is in contact with the protective cap and the first etch stop layer; and
forming a contact plug over the metal cap and in contact with the first etch stop layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein during forming the metal cap, the metal cap has a faster deposition rate on the source/drain contact than on the first etch stop layer.

### Claim 15 (depends on 13)

The method of claim 13, wherein the metal cap is selectively formed on the source/drain contact, such that a top surface of the first etch stop layer is free of coverage by the metal cap.

### Claim 16 (depends on 13)

The method of claim 13, further comprising:
forming a second etch stop layer over the first etch stop layer; and
forming an interlayer dielectric layer over the second etch stop layer, wherein the contact plug is formed through the interlayer dielectric layer and the second etch stop layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the contact plug comprises:
etching the interlayer dielectric layer and the second etch stop layer to form an opening exposing a top surface of the metal cap and a top surface of the first etch stop layer; and
filling the opening with a conductive material.

### Claim 18 (depends on 17)

The method of claim 17, wherein etching the interlayer dielectric layer and the second etch stop layer comprises etching a portion of the first etch stop layer.

### Claim 19 (depends on 1)

The semiconductor device of claim 1, further comprising:
a gate spacer along a sidewall of the gate structure; and
a protective cap spanning over the gate structure and the gate spacer, wherein a top surface of the metal cap is higher than a top surface of the protective cap.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the metal cap is in contact with the protective cap.