# US 12,224,323 B2 · Fabrication method of buried wordline structure

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- Number: US 12,224,323 B2
- Document ID: US12224323B2
- Status: Granted
- Kind: B2
- Application number: 17/445,595
- Filed: 2021-08-21
- Published: 2022-02-03
- Granted: 2025-02-11
- Earliest claimed: 2020-05-15
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Yong Lu; Hongkun Shen
- Web page: https://patentgrep.com/patent/US12224323B2

## CPC

- H10D 64/01: Manufacture or treatment
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- H10D 64/027: {by etching at gate locations}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/514: {characterised by the insulating layers}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10B 12/488: {Word lines}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A buried wordline structure fabrication method includes: providing a first trench in a semiconductor substrate, wherein the first trench has a tip on its bottom; performing epitaxial growth within the first trench to reduce the depth of the tip on the bottom of the first trench; and forming a gate dielectric layer on an inner wall of the first trench and filling a gate conductive layer within the first trench to form the buried wordline structure.

## Claims

### Claim 1

A fabrication method for a buried wordline structure, comprising:
providing a first trench in a semiconductor substrate, wherein the first trench has a tip on its bottom;
performing epitaxial growth on the semiconductor substrate within the first trench to reduce the depth of the tip on the bottom of the first trench; and
forming a gate dielectric layer on an inner wall of the first trench and filling a gate conductive layer within the first trench to form the buried wordline structure.

### Claim 2 (depends on 1)

The fabrication method according to claim 1, wherein a trench isolation structure is formed in the semiconductor substrate, and a surface layer of the semiconductor substrate is divided into a plurality of independent regions by the trench isolation structure; and before performing epitaxial growth within the first trench, the method further comprises:
providing a second trench in the trench isolation structure, wherein the second trench and the first trench are connected with each other, and the depth of the first trench is less than that of the second trench.

### Claim 3 (depends on 1)

The fabrication method according to claim 1, wherein a second trench has a tip on its bottom.

### Claim 4 (depends on 1)

The fabrication method according to claim 1, wherein a width of an opening of the first trench ranges from 30 nm to 50 nm, and a depth of the first trench ranges from 60 nm to 80 nm.

### Claim 5 (depends on 1)

The fabrication method according to claim 1, wherein
said providing a first trench in the semiconductor substrate comprises:
forming a mask layer on the semiconductor substrate and defining an etching window by the mask layer; and
etching the semiconductor substrate through the etching window to form the first trench; and
said performing the epitaxial growth within the first trench comprises:
using the mask layer as a protective layer to avoid performing epitaxial growth on the surface of the semiconductor substrate outside the first trench.

### Claim 6 (depends on 1)

The fabrication method according to claim 1, wherein prior to that the epitaxial growth is performed within the first trench, in-situ cleaning is performed on the inner wall of the first trench.

### Claim 7 (depends on 1)

The fabrication method according to claim 1, wherein said performing the epitaxial growth within the first trench to reduce the depth of the tip on the bottom of the first trench comprises: performing epitaxial growth within the first trench to reduce the depth of the tip until the tip disappears.

### Claim 8 (depends on 1)

The fabrication method according to claim 1, wherein said performing the epitaxial growth within the first trench comprises: performing chemical vapor phase epitaxy within the first trench, wherein reactant gases for the epitaxial growth comprise SiCl4 and H2.

### Claim 9 (depends on 1)

The fabrication method according to claim 1, wherein said forming the gate dielectric layer on the inner wall of the first trench and filling the gate conductive layer within the first trench comprises:
forming a gate dielectric layer on an inner wall of the first trench;
forming a conductive liner layer on the gate dielectric layer and filling a main conductive layer within the first trench, wherein the gate dielectric layer comprises the conductive liner layer and the main conductive layer; and
etching back the gate dielectric layer by utilizing an etching agent, wherein an etch selectivity ratio of the etching agent for the conductive liner layer and the main conductive layer is greater than 1, so that an upper surface of the etched gate dielectric layer is Ω-shaped.

### Claim 10 (depends on 9)

The fabrication method according to claim 9, wherein the etching back is anisotropic etching.

### Claim 11 (depends on 10)

The fabrication method according to claim 10, wherein the anisotropic etching is dry etching, and the etching agent comprises NF3 and Cl2.

### Claim 12

A buried wordline structure, comprising:
a semiconductor substrate;
a trench isolation structure, formed in the semiconductor substrate, wherein a surface layer of the semiconductor substrate is divided into a plurality of independent regions by the trench isolation structure;
a first trench, provided in the semiconductor substrate, wherein the first trench with an epitaxial layer formed on an inner wall thereof has a planar bottom;
a second trench, provided in the trench isolation structure, wherein the second trench has a tip on its bottom, the first trench and the second trench are connected with each other to form a connection trench, and the depth of the second trench is greater than that of the first trench;
a gate dielectric layer, formed on an inner wall of the first trench; and
a gate conductive layer, filled within the first trench and the second trench.

### Claim 13 (depends on 12)

The buried wordline structure according to claim 12, wherein an upper surface of the gate dielectric layer is Q-shaped.

### Claim 14 (depends on 12)

The buried wordline structure according to claim 12, wherein the width of an opening of the first trench ranges from 30 nm to 50 nm.

### Claim 15 (depends on 12)

The buried wordline structure according to claim 12, wherein the first trench has a filled epitaxial layer on its bottom to form a planar structure.