# US 12,224,319 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,319 B2 - Document ID: US12224319B2 - Status: Granted - Kind: B2 - Application number: 18/471,282 - Filed: 2023-09-20 - Published: 2024-01-11 - Granted: 2025-02-11 - Earliest claimed: 2017-12-14 - Assignees: Fuji Electric Co., Ltd. - Applicants: Fuji Electric Co., Ltd. - Inventors: Tatsuya Naito - Web page: https://patentgrep.com/patent/US12224319B2 ## CPC - H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current} - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 62/145: {Emitter regions of IGBTs} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 64/231: {Emitter or collector electrodes for bipolar transistors} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes a first-conductivity-type drift region provided in a semiconductor substrate; a trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, and extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate; a mesa portion provided in contact with the trench portion in an array direction orthogonal to the extending direction; a second-conductivity-type base region provided in the mesa portion above the drift region and in contact with the trench portion; and a second-conductivity-type floating region provided in the mesa portion below the base region, in contact with the trench portion, and provided in at least a part of the mesa portion in the array direction. ## Claims ### Claim 1 A semiconductor device comprising: a first-conductivity-type region provided in a semiconductor substrate; a trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, and extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate; a mesa portion provided in contact with the trench portion in an array direction orthogonal to the extending direction; a second-conductivity-type base region provided in the mesa portion above the drift region and in contact with the trench portion; a second-conductivity-type contact region provided in the mesa portion above the drift region and having a higher doping concentration than the base region; and a second-conductivity-type floating region provided in the mesa portion below the base region, in contact with the trench portion, and provided in at least a part of the mesa portion in the array direction, wherein the contact region extends in the extending direction over an end of the floating region in top view of the semiconductor substrate. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein at least a part of the floating region in a depth direction of the semiconductor substrate is provided in contact with a bottom portion of the trench portion. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein a remaining portion of the floating region other that at least the part of the floating region in the depth direction of the semiconductor substrate is arranged above the bottom portion of the trench portion. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, comprising: one or more first-conductivity-type emitter regions provided in the mesa portion above the drift region and having a higher doping concentration than the drift region. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the floating region is provided over a larger area in the extending direction than the emitter region. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein the emitter regions are discretely arranged in the extending direction. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein a length of the contact region is greater than a length of the emitter region in the extending direction. ### Claim 8 (depends on 4) The semiconductor device according to claim 4, comprising: a first-conductivity-type accumulation region provided in the mesa portion between the floating region and the base region and having a higher doping concentration than the drift region. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the accumulation region and an end of the floating region in the extending direction overlap in top view of the semiconductor substrate. ### Claim 10 (depends on 4) The semiconductor device according to claim 4, wherein a first floating region and a second floating region are provided in the mesa portion as the floating region; and an end of the first floating region and an end of the second floating region are arranged facing each other. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, comprising: another mesa portion adjacent to the mesa portion; wherein the base region is provided and no floating region is provided in the another mesa portion. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, wherein the contact region is provided in the another mesa portion. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein the contact region includes a contact hole, and the floating region is positioned closer to the trench portion than an end of the contact hole. ### Claim 14 A semiconductor device comprising: a first-conductivity-type region provided ion a semiconductor substrate; a trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, and extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate; a mesa portion provided in contact with the trench portion in an array direction orthogonal to the extending direction; a second-conductivity-type base region provided in the mesa portion above the drift region and in contact with the trench portion; and a second-conductivity-type floating region provided in the mesa portion below the base region, in contact with the trench portion, and provided in at least a part of the mesa portion in the array direction, wherein a first floating region and a second floating region are provided in the mesa portion as the floating region; an end of the first floating region in the extending direction and an end of the second floating region in the extending direction are arranged facing each other in the extending direction such that the drift region is provided between the first floating region and the second floating region. ### Claim 15 (depends on 14) The semiconductor device according to claim 14, wherein a gate trench portion and a dummy trench portion are provided at the trench portion. ### Claim 16 (depends on 14) The semiconductor device according to claim 14, wherein the mesa portion is between the gate trench portion and the dummy trench portion. ### Claim 17 (depends on 16) The semiconductor device according to claim 16, wherein the floating region is in contact with the gate trench portion. ### Claim 18 (depends on 16) The semiconductor device according to claim 16, wherein the floating region is in contact with the dummy trench portion. ### Claim 19 (depends on 16) The semiconductor device according to claim 16, wherein the floating region is in contact with the gate trench portion and is not in contact with the dummy trench portion. ### Claim 20 (depends on 14) The semiconductor device according to claim 14, comprising: a plurality of buffer regions provided below the drift region; wherein valleys are arranged between the plurality of buffer regions in a concentration distribution. ### Claim 21 A semiconductor device comprising: a first-conductivity-type drift region provided in a semiconductor substrate; a trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, and extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate; a mesa portion provided in contact with the trench portion in an array direction orthogonal to the extending direction; a second-conductivity-type base region provided in the mesa portion above the drift region and in contact with the trench portion; a second-conductivity-type contact region provided in the mesa portion above the drift region and having a higher doping concentration than the base region; a second-conductivity-type floating region provided in the mesa portion below the base region, in contact with the trench portion, and provided in at least a part of the mesa portion in the array direction; and a plurality of buffer regions provided below the drift region; wherein valleys are arranged between the plurality of buffer regions in a concentration distribution, and the contact region extends in the extending direction over an end of the floating region in top view of the semiconductor substrate. ### Claim 22 A semiconductor device comprising: a first-conductivity-type drift region provided in a semiconductor substrate; a trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, and extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate; a mesa portion provided in contact with the trench portion in an array direction orthogonal to the extending direction; a second-conductivity-type base region provided in the mesa portion above the drift region and in contact with the trench portion; a second-conductivity-type floating region provided in the mesa portion below the base region, in contact with the trench portion, and provided in at least a part of the mesa portion in the array direction; and a plurality of buffer regions provided below the drift region; wherein valleys are arranged between the plurality of buffer regions in a concentration distribution, and a gate trench portion and a dummy trench portion are provided as the trench portion.