# US 12,224,318 B2 · Radio frequency transistor amplifiers having self-aligned double implanted source/drain regions for improved on-resistance performance and related methods

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- Number: US 12,224,318 B2
- Document ID: US12224318B2
- Status: Granted
- Kind: B2
- Application number: 17/669,479
- Filed: 2022-02-11
- Published: 2023-08-17
- Granted: 2025-02-11
- Earliest claimed: 2022-02-11
- Assignees: Wolfspeed, Inc.
- Applicants: Wolfspeed, Inc.
- Inventors: Kyle Bothe; Chloe Hawes; Jennifer Gao; Scott Sheppard
- Web page: https://patentgrep.com/patent/US12224318B2

## CPC

- H10D 62/149: {Source or drain regions of field-effect devices}
- H10D 62/161: {of FETs having Schottky gates}
- H03F 1/0288: {using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers}
- H03F 1/56: Modifications of input or output impedances, not otherwise provided for
- H03F 3/195: in integrated circuits
- H03F 3/211: {using a combination of several amplifiers (H03F3/60 takes precedence)}
- H03F 3/245: {with semiconductor devices only}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 64/112: {comprising multiple field plate segments}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/22: using masks
- H03F 2200/222: A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
- H03F 2200/387: A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
- H03F 2200/451: the amplifier being a radio frequency amplifier
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/411: {for FETs}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H03F: AMPLIFIERS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A HEMT transistor has a semiconductor layer structure that comprises a Group III nitride-based channel layer and a higher bandgap Group III nitride-based barrier layer on the channel layer. A gate finger and first and second source/drain contacts are provided on the semiconductor layer structure. A first source/drain region is provided in the semiconductor layer structure that includes a first implanted region that is underneath the first source/drain contact and a first auxiliary implanted region. A depth of the first implanted region is at least twice a depth of the first auxiliary implanted a region. The first source/drain region extends inwardly a first distance from a lower edge of an inner sidewall of the first source/drain contact, and extends outwardly a second smaller distance from a lower edge of an outer sidewall of the first source/drain contact.

## Claims

### Claim 1

A method of forming a high electron mobility transistor, the method comprising:
forming a semiconductor layer structure that comprises a Group III nitride-based channel layer and a Group III nitride-based barrier layer that has a higher bandgap than the Group III nitride-based channel layer on an upper surface of the Group III nitride-based channel layer;
forming a photoresist on an upper surface of the semiconductor layer structure;
forming a first opening in the photoresist;
implanting ions into the semiconductor layer structure through the first opening to form a first implanted region in the semiconductor layer structure;
enlarging the first opening in the photoresist to create an expanded first opening;
implanting additional ions into the semiconductor layer structure through the expanded first opening using the photoresist as an ion implantation mask to form a first auxiliary implanted region in the semiconductor layer structure and to implant additional ions into the first implanted region,
wherein the first implanted region extends further into the semiconductor layer structure than does the first auxiliary implanted region.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first auxiliary implanted region merges into the first implanted region so that the first implanted region and the first auxiliary implanted region together form a first source/drain region in the semiconductor layer structure.

### Claim 3 (depends on 2)

The method of claim 2, the method further comprising:
forming a second opening in the photoresist simultaneously with forming the first opening;
implanting ions into the semiconductor layer structure through the second opening to form a second implanted region in the semiconductor layer structure simultaneously with forming the first implanted region, the second implanted region comprising at least a portion of a second source/drain region in the semiconductor layer structure;
forming a gate finger on an upper surface of the semiconductor layer structure, the gate finger defining a first longitudinal axis that extends parallel to the upper surface of the semiconductor layer structure;
forming a first source/drain contact on the first source/drain region; and
forming a second source/drain contact on the second source/drain region,
wherein the first source/drain contact, the second source/drain contact and the gate finger are the contacts of a first unit cell transistor.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first source/drain contact has an inner sidewall that faces the second source/drain contact and an outer sidewall opposite the inner sidewall, and the second source/drain contact has an inner sidewall that faces the first source/drain contact and an outer sidewall opposite the inner sidewall, and
wherein a second longitudinal axis that bisects a top surface of the first source/drain region and that is parallel to the first longitudinal axis is closer to the gate finger than is a third longitudinal axis that bisects a bottom surface of the first source/drain contact.

### Claim 5 (depends on 4)

The method of claim 4, wherein the first source/drain region has a variable depth, and the third longitudinal axis vertically overlaps a location where the first source/drain region has a maximum depth.

### Claim 6 (depends on 4)

The transistor of claim 4, wherein the first source/drain region has a variable doping density, and the third longitudinal axis vertically overlaps a location of a peak doping density of the first source/drain region.

### Claim 7 (depends on 4)

The transistor of claim 4, wherein the first auxiliary implanted region is closer to the gate finger than is the first implanted region.

### Claim 8 (depends on 3)

The method of claim 3, wherein the first source/drain region extends a first distance from a lower edge of the inner sidewall of the first source/drain contact towards the second source/drain region along a transverse axis that extends parallel to a plane defined by the upper surface of the semiconductor layer structure and perpendicular to the first longitudinal axis, and extends a second distance along the transverse axis from a lower edge of the outer sidewall of the first source/drain contact away from the second source/drain region, where the first distance is between 10% and 50% larger than the second distance.

### Claim 9 (depends on 8)

The method of claim 8, wherein the second source/drain region extends a third distance along the transverse axis from a lower edge of the inner sidewall of the second source/drain contact towards the first source/drain region, where the first distance is between 10% and 50% larger than the third distance.

### Claim 10 (depends on 8)

The method of claim 8, wherein the first source/drain region has a first width along the transverse axis and the second source/drain region has a second width along the transverse axis, where the first width exceeds the second width.

### Claim 11 (depends on 3)

The method of claim 3, further comprising a field plate that extends above an upper surface of the gate finger, the field plate being electrically connected to the second source/drain contact, wherein the field plate does not vertically overlap the first auxiliary implanted region.

### Claim 12 (depends on 1)

The method of claim 1, wherein a maximum doping density of the first implanted region exceeds a maximum doping density of the first auxiliary implanted region.

### Claim 13 (depends on 1)

The method of claim 1, wherein the first source/drain region is a drain region and the first source/drain contact is a drain contact.

### Claim 14 (depends on 1)

The method of claim 1, wherein an average sheet resistance of the first auxiliary implanted region is between 25% and 200% greater than an average sheet resistance of the first implanted region.

### Claim 15 (depends on 1)

The method of claim 1, wherein an average sheet resistance of a 2DEG channel region of the transistor is at least twice an average sheet resistance of the first auxiliary implanted region.

### Claim 16

A method of forming a high electron mobility transistor, the method comprising:
forming a semiconductor layer structure that comprises a Group III nitride-based channel layer and a Group III nitride-based barrier layer that has a higher bandgap than the Group III nitride-based channel layer on an upper surface of the Group III nitride-based channel layer;
forming a first source/drain region in the semiconductor layer structure, the first source/drain region including a first implanted region and a first auxiliary implanted region that merges with the first implanted region;
forming a second source/drain region in the semiconductor layer structure;
forming a gate finger on the semiconductor layer structure, the gate finger having a first longitudinal axis that extends parallel to an upper surface of the semiconductor layer structure;
forming a first source/drain contact on and above the first implanted region, the first source/drain contact having an inner sidewall that faces the gate finger and an outer sidewall opposite the inner sidewall;
forming a second source/drain contact on and above the second source/drain region, the second source/drain contact having an inner sidewall that faces the gate finger and an outer sidewall opposite the inner sidewall;
wherein a depth of the first implanted region is at least twice a depth of the first auxiliary implanted a region,
wherein the first source/drain region extends inwardly a first distance from a lower edge of the inner sidewall of the first source/drain contact towards the second source/drain region along a transverse axis that extends parallel to a plane defined by the upper surface of the semiconductor layer structure and perpendicular to the longitudinal axis, and extends outwardly a second distance along the transverse axis from a lower edge of the outer sidewall of the first source/drain contact away from the second source/drain region, where the first distance exceeds the second distance, and
wherein the first source/drain contact, the second source/drain contact and the gate finger are contacts of a first unit cell transistor.

### Claim 17 (depends on 16)

The method of claim 16, wherein the first distance is between 10% and 50% larger than the second distance.

### Claim 18 (depends on 17)

The method of claim 17, wherein a lower surface of the first source/drain contact is vertically aligned with the first implanted region.

### Claim 19 (depends on 18)

The method of claim 18, wherein the second source/drain region includes a second implanted region that is underneath the second source/drain contact and a second auxiliary implanted region that merges with the second implanted region.

### Claim 20 (depends on 19)

The method of claim 19, wherein a second longitudinal axis that is parallel to the first longitudinal axis that bisects a top surface of the first source/drain region is closer to the gate finger than is a third longitudinal axis that bisects a bottom surface of the first source/drain contact.

### Claim 21 (depends on 20)

The method of claim 20, wherein the third longitudinal axis vertically overlaps at least one of a location where the first source/drain region has a maximum depth and a location of a peak doping density of the first source/drain region.

### Claim 22 (depends on 18)

The method of claim 18, wherein the second source/drain region extends a third distance along the transverse axis from a lower edge of the inner sidewall of the second source/drain contact towards the first source/drain contact, where the first distance is between 10% and 50% larger than the third distance.

### Claim 23 (depends on 16)

The method of claim 16, wherein a maximum doping density of the first implanted region exceeds a maximum doping density of the first auxiliary implanted region.

### Claim 24 (depends on 16)

The method of claim 16, wherein the first source/drain region is a drain region and the first source/drain contact is a drain contact.

### Claim 25 (depends on 16)

The method of claim 16, wherein an average sheet resistance of the first auxiliary implanted region is between 25% and 200% greater than an average sheet resistance of the first implanted region.

### Claim 26 (depends on 16)

The method of claim 16, wherein an average sheet resistance of a 2DEG channel region of the transistor is at least twice an average sheet resistance of the first auxiliary implanted region.

### Claim 27

A method of forming a high electron mobility transistor, the method comprising:
forming a semiconductor layer structure that comprises a Group III nitride-based channel layer and a Group III nitride-based barrier layer that has a higher bandgap than the Group III nitride-based channel layer on an upper surface of the Group III nitride-based channel layer;
forming a carbon-containing mask on an upper surface of the semiconductor layer structure;
forming a first opening in the carbon-containing mask;
performing a first ion implantation process to implant ions into the semiconductor layer structure through the first opening;
changing a size the first opening in the carbon-containing mask to create a modified first opening; and
performing a second ion implantation process to implant additional ions into the semiconductor layer structure through the modified first opening using the carbon-containing mask as an ion implantation mask,
wherein the first and second ion implantation processes together form a first implanted region and a first auxiliary implanted region in the semiconductor layer structure, and
wherein the first implanted region and the first auxiliary implanted region together form a first source/drain region in the semiconductor layer structure and the first implanted region extends further into the semiconductor layer structure than does the first auxiliary implanted region.