# US 12,224,315 B2 · Semiconductor device

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- Number: US 12,224,315 B2
- Document ID: US12224315B2
- Status: Granted
- Kind: B2
- Application number: 17/516,900
- Filed: 2021-11-02
- Published: 2022-08-11
- Granted: 2025-02-11
- Earliest claimed: 2021-02-08
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Ju Hun Park; Won Cheol Jeong; Jin Wook Kim; Deok Han Bae; Myung Yoon Um; In Yeal Lee; Yoon Young Jung
- Web page: https://patentgrep.com/patent/US12224315B2

## CPC

- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes an active pattern extending in a first direction on a substrate, a gate structure on the active pattern and having a gate electrode extending in a second direction intersecting the active pattern, and a gate capping pattern on the gate electrode, the gate capping pattern including a gate capping liner defining a gate capping recess, the gate capping liner having a horizontal portion along an upper surface of the gate electrode, and a vertical portion extending from the horizontal portion in a third direction intersecting the first and second directions, and a gate capping filling film on the gate capping liner and filling the gate capping recess, an epitaxial pattern on the active pattern and adjacent the gate structure, a gate contact on and connected to the gate electrode, and an active contact on and connected to the epitaxial pattern.

## Claims

### Claim 1

A semiconductor device, comprising:
an active pattern extending in a first direction on a substrate;
a first gate structure on the active pattern, the first gate structure including:
a first gate electrode intersecting the active pattern, the first gate electrode extending in a second direction intersecting the first direction, and
a first gate capping pattern on the first gate electrode, the first gate capping pattern including:
a first lower gate capping liner defining a first gate capping recess, the first lower gate capping liner having a first horizontal portion extending along an upper surface of the first gate electrode, and a first vertical portion extending from the first horizontal portion in a third direction intersecting the first direction and the second direction, and
a first gate capping filling film on the first lower gate capping liner and filling the first gate capping recess;
a second gate structure extending in the second direction, the second gate structure being spaced apart from the first gate structure in the first direction;
a first epitaxial pattern on the active pattern, the first epitaxial pattern being between the first gate structure and the second gate structure;
a gate contact on and connected to the first gate electrode, wherein the first gate capping filing film is disposed in a space between the first lower gate capping liner and the gate contact; and
a first active contact on and connected to the first epitaxial pattern.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
a third gate structure extending in the second direction, the third gate structure being spaced apart from the second gate structure in the first direction, and the second gate structure being between the first gate structure and the third gate structure;
a second epitaxial pattern on the active pattern, the second epitaxial pattern being between the second gate structure and the third gate structure; and
a second active contact on and connected to the second epitaxial pattern, an upper surface of the second active contact being higher than an upper surface of the first active contact.

### Claim 3 (depends on 1)

The semiconductor device as claimed in claim 1,
wherein an upper surface of the first vertical portion is higher than an upper surface of the first active contact.

### Claim 4 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
a first upper gate capping liner on the first lower gate capping liner, an etching selectivity of the first lower gate capping liner and an etching selectivity of the first upper gate capping liner being different from each other.

### Claim 5 (depends on 4)

The semiconductor device as claimed in claim 4,
wherein the first lower gate capping liner includes aluminum.

### Claim 6 (depends on 1)

The semiconductor device as claimed in claim 1,
wherein the first gate structure includes a first gate spacer on side walls of the first gate electrode, at least a part of the first horizontal portion of the first lower gate capping liner overlapping an upper surface of the first gate spacer in the third direction.

### Claim 7 (depends on 1)

The semiconductor device as claimed in claim 1,
wherein the active pattern includes a fin-type pattern.

### Claim 8 (depends on 1)

The semiconductor device as claimed in claim 1,
wherein the active pattern includes a sheet pattern.

### Claim 9

A semiconductor device, comprising:
an active pattern extending in a first direction on a substrate;
a first gate structure on the active pattern, the first gate structure including:
a first gate electrode intersecting the active pattern, the first gate electrode extending in a second direction intersecting the first direction, and
a first gate capping pattern on the first gate electrode, the first gate capping pattern including:
a first lower gate capping liner defining a first gate capping recess, and
a first gate capping filling film on the first lower gate capping liner, the first gate capping filling film filling the first gate capping recess;
a second gate structure extending in the second direction, the second gate structure being spaced apart from the first gate structure in the first direction;
a first epitaxial pattern on the active pattern, the first epitaxial pattern being between the first gate structure and the second gate structure;
a first active contact on and connected to the first epitaxial pattern, the first lower gate capping liner being on a part of side walls of the first active contact and extending to an upper surface of the first active contact; and
a gate contact on and connected to the first gate electrode, wherein the first gate capping filing film is disposed in a space between the first lower gate capping liner and the gate contact.

### Claim 10 (depends on 9)

The semiconductor device as claimed in claim 9, further comprising:
a first upper gate capping liner on the first lower gate capping liner, an etching selectivity of the first lower gate capping liner and an etching selectivity of the first upper gate capping liner being different from each other.

### Claim 11 (depends on 10)

The semiconductor device as claimed in claim 10, wherein the first lower gate capping liner includes aluminum.

### Claim 12 (depends on 9)

The semiconductor device as claimed in claim 9, wherein the first lower gate capping liner includes:
a first horizontal portion extending along an upper surface of the first gate electrode, and
a first vertical portion extending from the first horizontal portion in a third direction intersecting the first direction and the second direction, an upper surface of the first vertical portion being on a same plane as the upper surface of the first active contact.

### Claim 13 (depends on 12)

The semiconductor device as claimed in claim 12, wherein the first vertical portion includes:
a first short vertical portion, and
a first long vertical portion spaced apart from the first short vertical portion in the first direction, the first long vertical portion being between the first short vertical portion and a side wall of the first active contact, and an upper surface of the first short vertical portion being lower than an upper surface of the first long vertical portion.

### Claim 14 (depends on 9)

The semiconductor device as claimed in claim 9, further comprising:
a third gate structure spaced apart from the first gate structure in the first direction, the first gate structure being between the second gate structure and the third gate structure;
a second epitaxial pattern between the first gate structure and the third gate structure; and
a second active contact on and connected to the second epitaxial pattern,
wherein the first lower gate capping liner includes a first horizontal portion extending along an upper surface of the first gate electrode, and a first vertical portion extending from the first horizontal portion in a third direction intersecting the first direction and the second direction, and
wherein an upper surface of the second active contact is lower than an upper surface of the first vertical portion.

### Claim 15 (depends on 9)

The semiconductor device as claimed in claim 9,
wherein the active pattern includes a fin-type pattern.

### Claim 16 (depends on 9)

The semiconductor device as claimed in claim 9,
wherein the active pattern includes a sheet pattern.

### Claim 17

A semiconductor device, comprising:
an active pattern extending in a first direction on a substrate;
a first gate structure on the active pattern, the first gate structure including:
a first gate electrode intersecting the active pattern, the first gate electrode extending in a second direction intersecting the first direction, and
a first gate capping pattern on the first gate electrode, the first gate capping pattern including a first gate capping liner defining a first gate capping recess, and a first gate capping filling film on the first gate capping liner and filling the first gate capping recess;
a second gate structure extending in the second direction, the second gate structure being spaced apart from the first gate structure in the first direction;
a third gate structure extending in the second direction, the third gate structure being spaced apart from the second gate structure in the first direction, and the second gate structure being between the first gate structure and the third gate structure;
a first epitaxial pattern on the active pattern, the first epitaxial pattern being between the first gate structure and the second gate structure;
a second epitaxial pattern on the active pattern, the second epitaxial pattern being between the second gate structure and the third gate structure;
a gate contact on and connected to the first gate electrode;
a first active contact on and connected to the first epitaxial pattern, a lower surface of the gate contact being higher than an upper surface of the first active contact; and
a second active contact on and connected to the second epitaxial pattern.

### Claim 18 (depends on 17)

The semiconductor device as claimed in claim 17, wherein an upper surface of the gate contact is on a same plane as an upper surface of the second active contact.

### Claim 19 (depends on 18)

The semiconductor device as claimed in claim 18, wherein the first gate capping liner includes:
a first lower gate capping liner; and
a first upper gate capping liner on the first lower gate capping liner, an etching selectivity of the first lower gate capping liner and an etching selectivity of the first upper gate capping liner being different from each other.

### Claim 20 (depends on 19)

The semiconductor device as claimed in claim 19, wherein the first lower gate capping liner includes aluminum.