# US 12,224,314 B2 · Size-controllable multi-stack semiconductor device and method of manufacturing the same

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- Number: US 12,224,314 B2
- Document ID: US12224314B2
- Status: Granted
- Kind: B2
- Application number: 17/402,214
- Filed: 2021-08-13
- Published: 2022-10-20
- Granted: 2025-02-11
- Earliest claimed: 2021-04-14
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Gunho Jo; Ki-il Kim; Byounghak Hong; Kang-ill Seo
- Web page: https://patentgrep.com/patent/US12224314B2

## CPC

- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 84/0128: {Manufacturing their channels}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/834: {comprising FinFETs}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A multi-stack semiconductor device includes: a substrate; and a plurality of multi-stack transistor structures arranged on the substrate in a channel width direction, wherein the multi-stack transistor structure include at least one lower transistor structure and at least one upper transistor structure stacked above the lower transistor structure, wherein the lower and upper transistor structures include at least one channel layer as a current channel, wherein the lower transistor structures of at least two multi-stack transistor structures have different channel-layer widths.

## Claims

### Claim 1

A multi-stack semiconductor device comprising:
a substrate; and
a plurality of multi-stack transistor structures arranged on the substrate in a channel width direction,
wherein the multi-stack transistor structures comprise at least one lower transistor structure and at least one upper transistor structure stacked above the lower transistor structure,
wherein the lower and upper transistor structures comprise at least one channel layer as a current channel, and
wherein the lower transistor structures of at least two multi-stack transistor structures have different channel-layer widths such that a width of a channel layer of a lower transistor structure is different from a width of a channel layer of another lower transistor structure, among the lower transistor structures.

### Claim 2 (depends on 1)

The multi-stack semiconductor device of claim 1,
wherein the upper transistor structures of the multi-stack transistor structures have a same channel-layer width or different channel-layer widths.

### Claim 3 (depends on 1)

The multi-stack semiconductor device of claim 1,
wherein the lower transistor structure of at least one multi-stack transistor structure has a greater channel-layer width than an upper transistor structure stacked thereabove, and
wherein the lower transistor structure of another at least one multi-stack transistor structure has a same channel-layer width as an upper transistor structure stacked thereabove.

### Claim 4 (depends on 3)

The multi-stack semiconductor device of claim 3, wherein a difference between channel-layer widths of the lower transistor structures of two multi-stack transistor structures is an integer multiple of a difference between channel-layer widths of the lower transistor structures of another two multi-stack transistor structures.

### Claim 5 (depends on 4)

The multi-stack semiconductor device of claim 4,
wherein each of the lower transistor structure and the upper transistor structure forms a nanosheet transistor structure.

### Claim 6 (depends on 4)

The multi-stack semiconductor device of claim 4,
wherein the lower transistor structure and the upper transistor structure form a nanosheet transistor structure and a fin-field effect transistor (finFET) structure, respectively.

### Claim 7 (depends on 1)

The multi-stack semiconductor device of claim 1,
wherein all of the upper transistor structures in the plurality of multi-stack transistor.

### Claim 8 (depends on 1)

The multi-stack semiconductor device of claim 1,
wherein a difference between channel-layer widths of the lower transistor structures of the two multi-stack nanosheet structures is an integer multiple of a difference between channel-layer widths of the lower transistor structures of another two multi-stack transistor structures.

### Claim 9 (depends on 1)

The multi-stack semiconductor device of claim 1,
wherein the lower transistor structure and the upper transistor structure form a nanosheet transistor structure and a fin-field effect transistor (finFET) structure, respectively.

### Claim 10

A multi-stack semiconductor device comprising:
a substrate; and
a plurality of multi-stack nanosheet structures arranged on the substrate in a channel width direction,
wherein the multi-stack nanosheet structures comprise at least one lower nanosheet stack and at least one upper nanosheet stack formed above the lower nanosheet stack,
wherein the lower and upper nanosheet stacks comprise a plurality of nanosheet layers as current channels for a transistor structure, and
wherein the lower nanosheet stacks of a 1st multi-stack nanosheet structure and a 2nd multi-stack nanosheet structure among the multi-stack nanosheet structures have different channel widths, corresponding to widths of the nanosheet layers, in a channel width direction.

### Claim 11 (depends on 10)

The multi-stack semiconductor device of claim 10,
wherein the upper nanosheet stacks of the multi-stack nanosheet structures have a same channel width or different channel widths.

### Claim 12 (depends on 10)

The multi-stack semiconductor device of claim 10,
wherein the lower nanosheet stacks of a 3rd multi-stack nanosheet structure and the 2nd multi-stack nanosheet structure among the multi-stack nanosheet structures have a same channel width.

### Claim 13 (depends on 12)

The multi-stack semiconductor device of claim 12,
wherein the lower nanosheet stacks of the 2nd and 3rd multi-stack nanosheet structures have a greater channel width than the upper nanosheet stacks of the 2nd and 3rd multi-stack nanosheet structures, respectively,
wherein, in the 2nd multi-stack nanosheet structure, left side surfaces of the nanosheet layers of the lower nanosheet stack are vertically coplanar with left side surfaces of the nanosheet layers of the upper nanosheet stack, and right side surfaces of the nanosheet layers of the lower nanosheet stack are protruded from a vertical plane of right side surfaces of the nanosheet layers of the upper nanosheet stack, and
wherein the 2nd and 3rd multi-stack nanosheet structures mirror-symmetric to each other in the channel width direction.

### Claim 14 (depends on 12)

The multi-stack semiconductor device of claim 12,
wherein the lower nanosheet stack of a 4th multi-stack nanosheet structure among the multi-stack nanosheet structures has a channel width greater than the channel widths of the lower nanosheet stacks the 1st to 3rd multi-stack nanosheet structures.

### Claim 15 (depends on 14)

The multi-stack semiconductor device of claim 14,
wherein in the 4th multi-stack nanosheet structure, left and right side surfaces of the nanosheet layers of the lower nanosheet stack are protruded from vertical planes of left and right side surfaces of the nanosheet layers of the upper nanosheet stack.

### Claim 16 (depends on 10)

The multi-stack semiconductor device of claim 10,
wherein the multi-stack nanosheet structures are connected to one another through the substrate which is a continuous structure without a connection mark.

### Claim 17

A method of manufacturing a multi-stack semiconductor device, the method comprising operations of:
(a) stacking at least one set of lower nanosheet layers and sacrificial layers, and at least one set of upper nanosheet layers and sacrificial layers in this order on a substrate;
(b) patterning the set of upper nanosheet layers and sacrificial layers to obtain a plurality of upper nanosheet stacks;
(c) conformally forming a 1st spacer layer on the upper nanosheet stacks;
(d) selectively removing the 1st spacer layer formed on sidewalls of the upper nanosheet stacks such that the 1st spacer layer on both sidewalls of a 1st upper nanosheet stack and only one of two sidewalls of a 2nd upper nanosheet stack are removed; and
(e) patterning the set of lower nanosheet layers and sacrificial layers using the remaining 1st spacer layer as mask to obtain a plurality of lower nanosheet stacks corresponding to the upper nanosheet stacks such that a width of a 2nd lower nanosheet stack patterned below the 2nd upper nanosheet stack is greater than a width of a 1st lower nanosheet stack patterned below the 1st upper nanosheet stack by a thickness of the 1st spacer layer.

### Claim 18 (depends on 17)

The method of claim 17,
wherein, in operation (d), the 1st spacer layer on only one of two sidewalls of a 3rd upper nanosheet stack is further removed, and
wherein, in operation (e), a 3rd lower nanosheet stack corresponding to the 3rd upper nanosheet stack is obtained such that a width of the 3rd lower nanosheet stack is the same as the width of the 2nd lower nanosheet stack.

### Claim 19 (depends on 18)

The method of claim 18,
wherein, in operation (d), the 1st spacer layer on both sidewalls of a 4th upper nanosheet stack is not removed, and
wherein, in operation (e), a 4th lower nanosheet stack corresponding to the 4th upper nanosheet stack is obtained such that a width of the 4th lower nanosheet stack is greater than the width of the 3rd lower nanosheet stack by the thickness of the 1st spacer layer.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
(c-1) conformally forming a 2nd spacer layer on a 5th upper nanosheet stack,
wherein, in operation (d), the 1st spacer layer and the 2nd spacer layer on both sidewalls of the 5th upper nanosheet stack are not removed, and
wherein, in operation (e), a 5th lower nanosheet stack corresponding to the 5th upper nanosheet stack is patterned using the remaining 1st spacer layer and 2nd spacer layer such that a width of the 5th lower nanosheet stack is greater than the 4th lower nanosheet stack by twice the thickness of the 2nd spacer layer.