# US 12,224,313 B2 · Semiconductor device and method for manufacturing the same

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- Number: US 12,224,313 B2
- Document ID: US12224313B2
- Status: Granted
- Kind: B2
- Application number: 18/197,600
- Filed: 2023-05-15
- Published: 2023-09-14
- Granted: 2025-02-11
- Earliest claimed: 2020-09-11
- Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
- Applicants: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
- Inventors: Yuhki Fujino
- Web page: https://patentgrep.com/patent/US12224313B2

## CPC

- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

According to one embodiment, a semiconductor device includes first and second electrodes, first to fifth semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode, and electrically connected to the first electrode. The second semiconductor region is provided on a part of the first semiconductor region. The third semiconductor region is provided on another part of the first semiconductor region. The third semiconductor region includes first and second regions. The fourth semiconductor region is provided on the second semiconductor region. The fifth semiconductor region is provided on a part of the fourth semiconductor region. The gate electrode faces the fourth semiconductor region with a gate insulating layer interposed between the gate electrode and the fourth semiconductor region. The second electrode is provided on the fourth and fifth semiconductor regions. The second electrode is electrically connected to the fourth and fifth semiconductor regions.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising:
forming a first diffusion region of a first conductivity type by doping an inner surface of an opening of a structural body with a first conductivity type impurity using plasma doping or solid phase diffusion, wherein:
the structural body includes:
a first semiconductor layer of the first conductivity type, and
a second semiconductor layer of the first conductivity type provided on the first semiconductor layer of the first conductivity type, an impurity concentration of the first conductivity type in the second semiconductor layer of the first conductivity type being lower than an impurity concentration of the first conductivity type in the first semiconductor layer of the first conductivity type, the opening being formed on an upper surface of the second semiconductor layer of the first conductivity type, and
the first diffusion region of the first conductivity type includes;
a first region separated from the inner surface of the opening of the structural body in a second direction perpendicular to a first direction, the first direction being from the first semiconductor layer of the first conductivity type to the second semiconductor layer of the first conductivity type, and
a second region positioned between the inner surface of the opening of the structural body and the first region, an impurity concentration of the first conductivity type in the second region being higher than an impurity concentration of the first conductivity type in the first region.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the first diffusion region includes a third region positioned between the first semiconductor layer of the first conductivity type and the inner surface of the opening of the structural body in the first direction.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the impurity concentration of the first conductivity type in the first region is less than 0.5 times the impurity concentration of the first conductivity type impurity in the second region.

### Claim 4 (depends on 1)

The method according to claim 1, further comprising forming a second diffusion region of a second conductivity type along the inner surface,
the second diffusion region of the second conductivity type being formed by doping a second conductivity type impurity along the inner surface of the opening of the structural body using plasma doping or solid phase diffusion.

### Claim 5 (depends on 4)

The method according to claim 4, further comprising:
forming a first insulating layer in the opening, and
forming a third diffusion region of the second conductivity type by ion-implantation on an upper portion of the second semiconductor layer of the first conductivity type.

### Claim 6 (depends on 5)

The method according to claim 5, wherein the first insulating layer includes a gap.

### Claim 7 (depends on 5)

The method according to claim 5, further comprising:
forming a gate electrode on the third diffusion region of the second conductivity type with interposed a second insulating layer therebetween, and
forming a fourth diffusion region of the first conductivity type by ion-implantation on an upper portion of the third diffusion region.

### Claim 8 (depends on 7)

The method according to claim 7, further comprising:
forming an electrode contacting the third diffusion region of the second conductivity type and the fourth diffusion region of the first conductivity type, and
forming another electrode contacting the first semiconductor layer.

### Claim 9 (depends on 4)

The method according to claim 4, wherein a length of the first diffusion region of the first conductivity type in the second direction is longer than a length of the second diffusion region of the second conductivity type in the second direction.

### Claim 10 (depends on 4)

The method according to claim 4, wherein:
the first region is separated from the second diffusion region of the second conductivity type in the second direction and a third direction,
the third direction is perpendicular to the first direction and intersects the second direction, and
the second region is provided between the second diffusion region and the first region in the second direction and the third direction.

### Claim 11 (depends on 1)

The method according to claim 1, wherein:
a plurality of openings is formed on the upper surface of the second semiconductor layer of the first conductivity type,
a length of one of the plurality of openings in a third direction is longer than a length of the one of the plurality of openings in the second direction, and
the third direction is perpendicular to the first direction and intersects the second direction.

### Claim 12 (depends on 1)

The method according to claim 1, wherein:
a plurality of openings is formed on the upper surface of the second semiconductor layer of the first conductivity type,
the plurality of openings arrayed in the second direction and a third direction, and
the third direction is perpendicular to the first direction and intersects the second direction.