# US 12,224,312 B2 · Field effect transistors with bottom dielectric isolation

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- Number: US 12,224,312 B2
- Document ID: US12224312B2
- Status: Granted
- Kind: B2
- Application number: 17/411,597
- Filed: 2021-08-25
- Published: 2023-03-02
- Granted: 2025-02-11
- Earliest claimed: 2021-08-25
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Julien Frougier; Ruilong Xie; Andrew M. Greene; Veeraraghavan S. Basker
- Web page: https://patentgrep.com/patent/US12224312B2

## CPC

- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/798: {being provided in or under the channel regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/364: {of IGFETs}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/834: {comprising FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device fabricated by forming FET fins from a layered semiconductor structure. The layered semiconductor structure incudes a sacrificial layer. Further by forming dummy gate structures on the FET fins, recessing the FET fins between dummy gate structures, growing source-drain regions between FET fins and the sacrificial layer, replacing active region dummy gate structures with high-k metal gates structures, and replacing the sacrificial layer with a dielectric isolation material, wherein the dielectric isolation material extends across the active region.

## Claims

### Claim 1

A field effect transistor (FET) device comprising:
an active region, the active region comprising a plurality of field effect transistors, a first edge and a second edge disposed opposite the first edge;
a dielectric isolation region disposed horizontally-beneath the active region and above an underlying semiconductor substrate, the dielectric isolation region further disposed vertically in gate diffusion break regions at the first edge and the second edge of the active region.

### Claim 2 (depends on 1)

The FET device according to claim 1, wherein the dielectric isolation region is disposed vertically at two edges of the active region.

### Claim 3 (depends on 1)

The FET device according to claim 1, wherein the dielectric isolation region comprises an air gap.

### Claim 4 (depends on 3)

The FET device according to claim 3, wherein an air gap cross section corresponds to an aspect ratio of horizontal and vertical dielectric isolation portions.

### Claim 5 (depends on 1)

The FET device according to claim 1, wherein the dielectric isolation region comprises a plurality of air gaps.

### Claim 6 (depends on 1)

The FET device according to claim 1, further comprising a plurality of finFET devices.

### Claim 7 (depends on 1)

The FET device according to claim 1, further comprising a plurality of gate-all-around devices.

### Claim 8 (depends on 1)

The FET device according to claim 1 further comprising a stressed source-drain region disposed between the dielectric isolation region and a channel of the FET.

### Claim 9 (depends on 1)

The FET according to claim 1, wherein the horizontal and vertical dielectric isolation regions comprise a continuous dielectric isolation region.

### Claim 10 (depends on 1)

The FET according to claim 1, wherein the dielectric isolation region exhibits one of tensile or compressive stress properties.