# US 12,224,310 B2 · Single-crystal transistors for memory devices

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- Number: US 12,224,310 B2
- Document ID: US12224310B2
- Status: Granted
- Kind: B2
- Application number: 18/531,525
- Filed: 2023-12-06
- Published: 2024-03-28
- Granted: 2025-02-11
- Earliest claimed: 2021-07-02
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Fatma Arzum Simsek-Ege; Masihhur R. Laskar; Nicholas R. Tapias; Darwin Franseda Fan; Manuj Nahar
- Web page: https://patentgrep.com/patent/US12224310B2

## CPC

- H10D 62/40: Crystalline structures
- H10P 14/276: {Lateral overgrowth}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/274: {using seed materials}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/50: {Peripheral circuit region structures}
- H10B 53/30: characterised by the memory core region
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

## Claims

### Claim 1

An apparatus, comprising:
a dielectric portion;
a semiconductor portion in contact with a top surface of the dielectric portion and extending into the dielectric portion with a tapered projection, the semiconductor portion comprising a single-grain crystalline arrangement;
a first transistor terminal in contact with a top surface of the semiconductor portion at a first location;
a second transistor terminal in contact with the top surface of the semiconductor portion at a second location;
a transistor gate dielectric in contact with the top surface of the semiconductor portion at a third location between the first location and the second location; and
a transistor gate conductor in contact with a top surface of the transistor gate dielectric.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the semiconductor portion comprises:
a first doped region in contact with the first transistor terminal; and
a second doped region in contact with the second transistor terminal.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the dielectric portion comprises:
a first dielectric layer having a first thermal conductivity; and
a second dielectric layer over the first dielectric layer, the second dielectric layer having a second thermal conductivity that is less than the first thermal conductivity.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein:
the first dielectric layer comprises an oxide material; and
the second dielectric layer comprises a nitride material.

### Claim 5 (depends on 1)

The apparatus of claim 1, further comprising:
a material portion between an end of the tapered projection of the semiconductor portion and the dielectric portion, the material portion comprising silicon-germanium, nickel, a metal silicide, or polysilicon.

### Claim 6

An apparatus, comprising:
a deck of memory cells;
a dielectric portion above the deck of memory cells; and
a plurality of transistors coupled with the deck of memory cells, wherein each transistor of the plurality of transistors comprises:
a semiconductor portion in contact with a top surface of the dielectric portion, the semiconductor portion comprising a single-grain crystalline arrangement and having a tapered extension into the dielectric portion;
a first terminal in contact with a first portion of a top surface of the semiconductor portion;
a second terminal in contact with a second portion of the top surface of the semiconductor portion; and
a gate conductor operable to modulate a conductivity of the semiconductor portion between the first terminal and the second terminal.

### Claim 7 (depends on 6)

The apparatus of claim 6, further comprising:
a second dielectric material between each of the plurality of transistors, wherein each sidewall of the second dielectric material is in contact with a sidewall of the semiconductor portion and a bottom surface of the second dielectric material is in contact with a top surface of the dielectric portion.

### Claim 8 (depends on 6)

The apparatus of claim 6, wherein, for each of the plurality of transistors, the semiconductor portion comprises:
a first doped region in contact with the first terminal; and
a second doped region in contact with the second terminal.

### Claim 9 (depends on 6)

The apparatus of claim 6, wherein the dielectric portion comprises:
a first dielectric layer having a first thermal conductivity; and
a second dielectric layer over the first dielectric layer, the second dielectric layer having a second thermal conductivity that is less than the first thermal conductivity.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein:
the first dielectric layer comprises an oxide material; and
the second dielectric layer comprises a nitride material.

### Claim 11 (depends on 6)

The apparatus of claim 6, further comprising:
a material portion between an end of the tapered extension of the semiconductor portion and the dielectric portion, the material portion comprising silicon-germanium, nickel, a metal silicide, or polysilicon.

### Claim 12

A transistor formed by a process of:
forming a cavity extending through at least a portion of one or more dielectric materials, wherein the cavity includes a taper from a first cross-sectional area toward a point;
depositing a semiconductor material in the cavity and above the one or more dielectric materials;
forming the semiconductor material in a single crystalline arrangement based at least in part on heating and cooling the semiconductor material; and
forming a channel portion of the transistor based at least in part on doping the single crystalline arrangement of the semiconductor material.

### Claim 13 (depends on 12)

The transistor of claim 12, wherein the single crystalline arrangement of the semiconductor material is formed by the process comprising:
nucleating the single crystalline arrangement of the semiconductor material at a nucleation site at an end of the cavity opposite from an opening of the cavity.

### Claim 14 (depends on 12)

The transistor of claim 12, wherein heating the semiconductor material comprises:
applying a laser to the semiconductor material.

### Claim 15 (depends on 12)

The transistor of claim 12, wherein the taper of the cavity is associated with an included angle that is between 35 degrees and 55 degrees.

### Claim 16 (depends on 12)

The transistor of claim 12, wherein a cross-sectional area of the cavity at an end opposite from an opening of the cavity has a width of less than or equal to 7 nanometers.

### Claim 17 (depends on 12)

The transistor of claim 12, formed by the process comprising:
depositing the semiconductor material with an amorphous arrangement or a polycrystalline arrangement.

### Claim 18 (depends on 12)

The transistor of claim 12, formed by the process further comprising:
depositing, in the cavity, a second material before depositing the semiconductor material, wherein forming the single crystalline arrangement of the semiconductor material is based at least in part on a nucleation of the single crystalline arrangement at an interface between the second material and the semiconductor material.

### Claim 19 (depends on 12)

The transistor of claim 12, formed by the process further comprising:
forming the one or more dielectric materials based at least in part on depositing a first dielectric material and depositing a second dielectric material over the first dielectric material, wherein forming the cavity comprises forming the cavity with the taper through at least a portion of the first dielectric material.

### Claim 20 (depends on 19)

The transistor of claim 19, wherein:
the first dielectric material has a first thermal conductivity; and
the second dielectric material has a second thermal conductivity that is less than the first thermal conductivity.