# US 12,224,295 B2 · Image sensor and method of manufacturing the same

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- Number: US 12,224,295 B2
- Document ID: US12224295B2
- Status: Granted
- Kind: B2
- Application number: 17/455,246
- Filed: 2021-11-17
- Published: 2022-09-15
- Granted: 2025-02-11
- Earliest claimed: 2021-03-10
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Hakyu Choi; Yongsuk Choi; Keo-Sung Park; Dongwook Won
- Web page: https://patentgrep.com/patent/US12224295B2

## CPC

- H10F 39/80373: {characterised by the gate of the transistor}
- H10F 39/014: {of CMOS image sensors}
- H10F 39/182: {Colour image sensors}
- H10F 39/199: {Back-illuminated image sensors}
- H10F 39/8053: {Colour filters}
- H10F 39/8063: {Microlenses}
- H10F 39/807: {Pixel isolation structures}
- H10F 39/811: {Interconnections}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

A method of manufacturing an image sensor includes forming a first dopant region having a second conductivity type in a semiconductor substrate including first and second surfaces. The semiconductor substrate has a first conductivity type different from the second conductivity type. The method further includes forming a pixel isolation structure defining pixel regions in the semiconductor substrate, forming a vertical trench by patterning the first surface in each of the pixel regions, forming a mask pattern exposing each of the pixel regions on the first surface, in which the mask pattern includes a residual mask pattern filling at least a portion of the vertical trench, forming a second dopant region having the second conductivity type in the semiconductor substrate by using the mask pattern as an ion-implantation mask, in which the second dopant region is adjacent to the vertical trench, and forming a transfer gate electrode in the vertical trench.

## Claims

### Claim 1

A method of manufacturing an image sensor, the method comprising:
forming a first dopant region having a second conductivity type in a semiconductor substrate,
wherein the semiconductor substrate comprises a first surface and a second surface opposite to the first surface, and the semiconductor substrate has a first conductivity type different from the second conductivity type;
forming a pixel isolation structure defining a plurality of pixel regions in the semiconductor substrate;
forming a vertical trench by patterning the first surface of the semiconductor substrate in each of the pixel regions;
forming a mask pattern exposing each of the pixel regions on the first surface of the semiconductor substrate, wherein the mask pattern comprises a residual mask pattern filling at least a portion of the vertical trench;
forming a second dopant region by ion-implanting dopants having the second conductivity type into the semiconductor substrate by using the mask pattern as an ion-implantation mask, wherein the second dopant region is adjacent to the vertical trench; and
forming a transfer gate electrode in the vertical trench, wherein a gate insulating layer is interposed between the transfer gate electrode and an inner surface of the vertical trench.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second dopant region comprises:
a first region adjacent to a sidewall of the vertical trench; and
a second region adjacent to a bottom surface of the vertical trench,
wherein an ion-implantation depth of the dopants in the second region is different from an ion-implantation depth of the dopants in the first region.

### Claim 3 (depends on 1)

The method of claim 1, wherein the residual mask pattern completely fills the vertical trench.

### Claim 4 (depends on 1)

The method of claim 1, wherein the residual mask pattern has a thickness equal to a half of a depth of the vertical trench.

### Claim 5 (depends on 1)

The method of claim 1, wherein the residual mask pattern has a non-uniform thickness in the vertical trench.

### Claim 6 (depends on 1)

The method of claim 1, wherein the second dopant region comprises:
a first region adjacent to a sidewall of the vertical trench; and
a second region adjacent to a bottom surface of the vertical trench,
wherein a concentration of the dopants having the second conductivity type has a maximum value in the first region of the second dopant region.

### Claim 7 (depends on 1)

The method of claim 1, wherein the second dopant region comprises:
a first region adjacent to a sidewall of the vertical trench; and
a second region adjacent to a bottom surface of the vertical trench,
wherein a concentration of the dopants having the second conductivity type is uniform in the first region and the second region at a same distance from the first surface of the semiconductor substrate.

### Claim 8 (depends on 1)

The method of claim 1, wherein the second dopant region comprises:
a first region adjacent to a sidewall of the vertical trench; and
a second region adjacent to a bottom surface of the vertical trench,
wherein a distance between a bottom surface of the transfer gate electrode and the second region is less than a distance between the first surface of the semiconductor substrate and the first region.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
forming a device isolation layer adjacent to the first surface in the semiconductor substrate before forming the vertical trench,
wherein a bottom surface of the device isolation layer is closer to the first surface of the semiconductor substrate than a bottom surface of the vertical trench.

### Claim 10 (depends on 9)

The method of claim 9, wherein the first dopant region overlaps the device isolation layer and the transfer gate electrode.

### Claim 11 (depends on 1)

The method of claim 1, wherein a width of the second dopant region is less than a width of the first dopant region.

### Claim 12 (depends on 1)

The method of claim 1, wherein a concentration of the dopants having the second conductivity type is greater in the second dopant region than in the first dopant region.