# US 12,224,293 B2 · Oxide semiconductor device

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- Number: US 12,224,293 B2
- Document ID: US12224293B2
- Status: Granted
- Kind: B2
- Application number: 18/399,990
- Filed: 2023-12-29
- Published: 2024-05-16
- Granted: 2025-02-11
- Earliest claimed: 2018-04-12
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Shunpei Yamazaki; Yuichi Sato; Hitoshi Nakayama
- Web page: https://patentgrep.com/patent/US12224293B2

## CPC

- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10D 86/60: wherein the TFTs are in active matrices
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 41/70: the floating gate being an electrode shared by two or more components
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/80: characterised by the materials
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 88/01: {Manufacture or treatment}
- H10W 20/076: {in via holes or trenches}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/496: {Capacitor integral with wiring layers}
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device including: a first insulator in which an opening is formed; a first conductor positioned in the opening; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a second conductor over the third oxide and the first conductor; a third conductor over the fourth oxide; a fifth oxide over the second oxide; a second insulator over the fifth oxide; and a fourth conductor positioned over the second insulator and overlapping with the fifth oxide. The fifth oxide is in contact with each of a side surface of the third oxide and a side surface of the fourth oxide. The conductivity of the third oxide is higher than the conductivity of the second oxide. The second conductor is in contact with the top surface of the first conductor.

## Claims

### Claim 1

A semiconductor device comprising:
a first insulator;
a first conductor in an opening in the first insulator;
a transistor electrically connected to the first conductor, the transistor comprising:
a first oxide semiconductor over the first insulator;
a second oxide semiconductor over the first oxide semiconductor;
a third oxide semiconductor over the second oxide semiconductor;
a source electrode in contact with a first side surface of the first oxide semiconductor and a first side surface of the second oxide semiconductor;
a drain electrode in contact with a second side surface of the first oxide semiconductor and a second side surface of the second oxide semiconductor; and
a gate electrode over the third oxide semiconductor;
a second insulator over the source electrode and the drain electrode;
a second conductor in a first opening in the second insulator; and
a third insulator in the first opening in the second insulator,
wherein the third insulator is in contact with a side surface of the second conductor,
wherein the first conductor and one of the source electrode and the drain electrode overlap each other,
wherein the third oxide semiconductor and the gate electrode are provided in a second opening in the second insulator, and
wherein the second conductor and the first conductor overlap each other.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the first conductor is in contact with the one of the source electrode and the drain electrode.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the source electrode and the drain electrode are in contact with the third oxide semiconductor.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the second conductor is provided over and in contact with the one of the source electrode and the drain electrode.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the source electrode, the drain electrode, and the first oxide semiconductor are in direct contact with the first insulator.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the third oxide semiconductor is in contact with the first oxide semiconductor.

### Claim 7

A semiconductor device comprising:
a first insulator;
a first conductor in an opening in the first insulator;
a transistor electrically connected to the first conductor, the transistor comprising:
a first oxide semiconductor over the first insulator;
a second oxide semiconductor over the first oxide semiconductor;
a first oxide over the second oxide semiconductor;
a second oxide over the second oxide semiconductor;
a third oxide semiconductor over the second oxide semiconductor;
a source electrode in contact with a first side surface of the first oxide semiconductor, a first side surface of the second oxide semiconductor, and the first oxide;
a drain electrode in contact with a second side surface of the first oxide semiconductor, a second side surface of the second oxide semiconductor, and the second oxide; and
a gate electrode over the third oxide semiconductor;
a second insulator over the source electrode and the drain electrode;
a second conductor in a first opening in the second insulator; and
a third insulator in the first opening in the second insulator,
wherein the third insulator is in contact with a side surface of the second conductor,
wherein the first conductor and one of the source electrode and the drain electrode overlap each other,
wherein the third oxide semiconductor and the gate electrode are provided in a second opening in the second insulator, and
wherein the second conductor and the first conductor overlap each other.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein the first conductor is in contact with the one of the source electrode and the drain electrode.

### Claim 9 (depends on 7)

The semiconductor device according to claim 7, wherein the source electrode and the drain electrode are in contact with the third oxide semiconductor.

### Claim 10 (depends on 7)

The semiconductor device according to claim 7, wherein the second conductor is provided over and in contact with the one of the source electrode and the drain electrode.

### Claim 11 (depends on 7)

The semiconductor device according to claim 7, wherein the source electrode, the drain electrode, and the first oxide semiconductor are in direct contact with the first insulator.

### Claim 12 (depends on 7)

The semiconductor device according to claim 7, wherein the third oxide semiconductor is in contact with the first oxide semiconductor.

### Claim 13

A semiconductor device comprising:
a first insulator;
a first conductor in an opening in the first insulator;
a transistor electrically connected to the first conductor, the transistor comprising:
a first oxide semiconductor over the first insulator;
a second oxide semiconductor over the first oxide semiconductor;
a first oxide over and in contact with the second oxide semiconductor;
a second oxide over and in contact with the second oxide semiconductor;
a third oxide semiconductor over the second oxide semiconductor;
a source electrode in contact with a first side surface of the first oxide semiconductor, a first side surface of the second oxide semiconductor, and the first oxide;
a drain electrode in contact with a second side surface of the first oxide semiconductor, a second side surface of the second oxide semiconductor, and the second oxide; and
a gate electrode over the third oxide semiconductor;
a second insulator over the source electrode and the drain electrode;
a second conductor in a first opening in the second insulator; and
a third insulator in the first opening in the second insulator,
wherein the third insulator is in contact with a side surface of the second conductor,
wherein the first conductor and one of the source electrode and the drain electrode overlap each other,
wherein the third oxide semiconductor and the gate electrode are provided in a second opening in the second insulator, and
wherein the second conductor and the first conductor overlap each other.

### Claim 14 (depends on 13)

The semiconductor device according to claim 13, wherein the first conductor is in contact with the one of the source electrode and the drain electrode.

### Claim 15 (depends on 13)

The semiconductor device according to claim 13, wherein the source electrode and the drain electrode are in contact with the third oxide semiconductor.

### Claim 16 (depends on 13)

The semiconductor device according to claim 13, wherein the second conductor is provided over and in contact with the one of the source electrode and the drain electrode.

### Claim 17 (depends on 13)

The semiconductor device according to claim 13, wherein the source electrode, the drain electrode, and the first oxide semiconductor are in direct contact with the first insulator.

### Claim 18 (depends on 13)

The semiconductor device according to claim 13, wherein the third oxide semiconductor is in contact with the first oxide semiconductor.