# US 12,224,292 B2 · Array substrate, display panel, and manufacturing method of array substrate

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,224,292 B2
- Document ID: US12224292B2
- Status: Granted
- Kind: B2
- Application number: 17/624,033
- Filed: 2021-12-27
- Published: 2023-06-22
- Granted: 2025-02-11
- Earliest claimed: 2021-12-17
- Assignees: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Inventors: Chen Dai
- Web page: https://patentgrep.com/patent/US12224292B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10D 84/01: Manufacture or treatment
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D 86/01: Manufacture or treatment
- H10D 86/021: {of multiple TFTs}
- H10D 86/0212: {comprising manufacture, treatment or coating of substrates}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/0223: {comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/674: {characterised by the active materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An array substrate, a display panel, and a manufacturing method of the array substrate are disclosed. The array substrate includes a substrate and a thin film transistor layer. The thin film transistor layer includes a first thin film transistor, and the first thin film transistor includes a first active layer, a first gate insulating layer, a first source and drain electrode layer, and a first gate electrode disposed on a same layer as the first source and drain electrode layer. Disposing the first gate electrode on the same layer as the first source and drain electrode layer can simplify manufacturing processes.

## Claims

### Claim 1

An array substrate, comprising:
a substrate; and
a thin film transistor layer disposed on the substrate;
wherein the thin film transistor layer comprises a first thin film transistor, and the first thin film transistor comprises a first active layer, a first gate insulating layer, and a first source and drain electrode layer disposed in a stack on the substrate;
the first gate insulating layer is disposed between the first active layer and the first source and drain electrode layer, and the first source and drain electrode layer comprises a first source electrode and a first drain electrode electrically connected to the first active layer; and
the first thin film transistor further comprises a first gate electrode disposed on the first gate insulating layer, and the first gate electrode and the first source and drain electrode layer are disposed on a same layer;
wherein the first thin film transistor further comprises a second gate electrode and an interlayer insulating layer, the second gate electrode is disposed on one side of the first active layer adjacent to the substrate, and the interlayer insulating layer is disposed between the first active layer and the second gate electrode.

### Claim 2 (depends on 1)

The array substrate according to claim 1, wherein the first active layer, the first gate insulating layer, and the first source and drain electrode layer are disposed in sequence in a direction away from the substrate.

### Claim 3 (depends on 1)

The array substrate according to claim 1, wherein gaps are defined between the first gate electrode and the first source electrode and between the first gate electrode and the first drain electrode, and the first gate insulating layer corresponding to the gaps is defined with first vias.

### Claim 4 (depends on 3)

The array substrate according to claim 3, further comprising a planarization layer disposed on the first source and drain electrode layer and the first gate electrode and filled in the gaps and the first vias.

### Claim 5 (depends on 1)

The array substrate according to claim 1, further comprising a second thin film transistor disposed in parallel with the first thin film transistor on the substrate;
wherein the second thin film transistor comprises a second active layer, the first gate insulating layer, and a second source and drain electrode layer disposed in a stack on the substrate;
the first gate insulating layer is disposed between the second active layer and the second source and drain electrode layer, and the second source and drain electrode layer comprises a second source electrode and a second drain electrode electrically connected to the second active layer; and
the second source and drain electrode layer, the first source and drain electrode layer, and the first gate electrode are disposed on the same layer.

### Claim 6 (depends on 5)

The array substrate according to claim 5, wherein the second active layer, the first gate insulating layer, and the second source and drain electrode layer are disposed in sequence in a direction away from the substrate.

### Claim 7 (depends on 5)

The array substrate according to claim 5, wherein the first gate insulating layer corresponding to the first source electrode is defined with a second via, the second via exposes the second active layer, and the first source electrode is electrically connected to the second active layer by the second via.

### Claim 8 (depends on 5)

The array substrate according to claim 5, wherein the second thin film transistor comprises a third gate electrode and a second gate insulating layer, the third gate electrode is disposed corresponding to the second active layer, and the second gate insulating layer is disposed between the third gate electrode and the second active layer; and
the third gate electrode is disposed on one side of the second active layer away from the substrate or on one side of the second active layer adjacent to the substrate.

### Claim 9 (depends on 8)

The array substrate according to claim 8, further comprising a light shielding metal layer disposed on the side of the second active layer adjacent to the substrate.

### Claim 10 (depends on 8)

The array substrate according to claim 8, wherein the third gate electrode is disposed on a same layer as the second gate electrode or with the first source and drain electrode layer.

### Claim 11 (depends on 8)

The array substrate according to claim 8, wherein the second thin film transistor further comprises a fourth gate electrode and a third gate insulating layer, the third gate insulating layer is disposed between the third gate 30 electrode and the fourth gate electrode, and the fourth gate electrode is disposed corresponding to the second active layer.

### Claim 12 (depends on 11)

The array substrate according to claim 11, wherein the third gate electrode and the fourth gate electrode are disposed on the side of the second active layer away from the substrate, or at least one of the third gate electrode or the fourth gate electrode is disposed on the side of the second active layer adjacent to the substrate.

### Claim 13 (depends on 5)

The array substrate according to claim 5, wherein a material of the first active layer comprises one or more of indium gallium zinc oxide, indium tin oxide, or indium zinc oxide, and a material of the second active layer comprises low temperature polysilicon.

### Claim 14 (depends on 1)

A display panel, comprising the array substrate according to claim 1.

### Claim 15

A manufacturing method of an array substrate, comprising following steps:
providing a substrate;
disposing a first active layer and a first gate insulating layer in sequence on the substrate; and
forming a first gate electrode, a first source electrode, and a first drain electrode on the first gate insulating layer and allowing the first source electrode and the first drain electrode to be electrically connected to the first active layer, wherein the first active layer, the first gate insulating layer, the first gate electrode, the first source electrode, and the first drain electrode form a first thin film transistor;
wherein the step of disposing the first active layer and the first gate insulating layer in sequence on the substrate comprises following steps:
disposing a second active layer and a second gate insulating layer in sequence on the substrate;
forming a second gate electrode and a third gate electrode on the second gate insulating layer and allowing the third gate electrode to correspond to the second active layer;
disposing an interlayer insulating layer on the second gate electrode and the third gate electrode;
forming the first active layer on the interlayer insulating layer corresponding to the second gate electrode; and
disposing the first gate insulating layer on the first active layer.

### Claim 16 (depends on 15)

The manufacturing method of the array substrate according to claim 15, wherein the step of forming the first gate electrode, the first source electrode, and the first drain electrode on the first gate insulating layer comprises following steps:
forming the first gate electrode, the first source electrode, the first drain electrode, a second source electrode, and a second drain electrode on the first gate insulating layer, allowing the first source electrode and the first drain electrode to be electrically connected to the first active layer, and allowing the first source electrode, the second source electrode, and the second drain electrode to be electrically connected to the second active layer, wherein the second active layer, the second gate insulating layer, the third gate electrode, the first gate insulating layer, the second source electrode, and the second drain electrode form a second thin film transistor.

### Claim 17 (depends on 16)

The manufacturing method of the array substrate according to claim 16, further comprising a following step:
disposing a planarization layer on the first gate electrode, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode.

### Claim 18 (depends on 15)

The manufacturing method of the array substrate according to claim 15, wherein before the step of disposing the second active layer and the second gate insulating layer in sequence on the substrate, the method further comprises following steps:
disposing a light shielding metal layer on the substrate; and
disposing a buffer layer on the light shielding metal layer.