# US 12,224,288 B2 · Array base plate, method for manufacturing same, and display panel

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- Number: US 12,224,288 B2
- Document ID: US12224288B2
- Status: Granted
- Kind: B2
- Application number: 17/620,678
- Filed: 2021-11-12
- Published: 2024-02-08
- Granted: 2025-02-11
- Earliest claimed: 2021-10-26
- Assignees: Huizhou China Star Optoelectronics Display Co., Ltd.; Tcl China Star Optoelectronics Technology Co., Ltd.
- Applicants: Huizhou China Star Optoelectronics Display Co., Ltd.; TCL China Star Optoelectronics Technology Co., Ltd.
- Inventors: Jiahui Huang
- Web page: https://patentgrep.com/patent/US12224288B2

## CPC

- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An array base plate, a method for manufacturing same, and a display panel are disclosed. The array base plate includes: an active layer including a body portion, and a first conduction portion and a second conduction portion disposed on two sides of the active layer; an etching protective layer and an ohmic contact layer disposed in a same layer, where the etching protective layer is located on the body portion, and the ohmic contact layer is located on the first conduction portion and the second conduction portion; and a source and a drain separately disposed on the ohmic contact layer located on the first conduction portion and the second conduction portion.

## Claims

### Claim 1

An array base plate, comprising:
a substrate;
an active layer disposed on the substrate;
an etching protective layer and an ohmic contact layer, wherein the etching protective layer and the ohmic contact layer are disposed in a same layer, the etching protective layer is located on a body portion of the active layer, and the ohmic contact layer is located on a first conduction portion and a second conduction portion of the active layer;
a source disposed on the ohmic contact layer located on the first conduction portion of the active layer; and
a drain disposed on the ohmic contact layer located on the second conduction portion of the active layer;
wherein a material of the ohmic contact layer comprises a metal or metal oxide, and a material of the etching protective layer comprises an Si-based insulating material.

### Claim 2 (depends on 1)

The array base plate according to claim 1, wherein the active layer comprises an active portion and a protective portion sequentially disposed in a stacked manner, and a mobility of the active portion is greater than a mobility of the protective portion.

### Claim 3 (depends on 1)

The array base plate according to claim 1, wherein the material of the ohmic contact layer comprises one or a combination of more than one of Si, ITO, Mo, Al, Ti, or Cu, and the material of the etching protective layer comprises one or a combination of more than one of silicon nitride, silicon oxynitride, or silicon oxide.

### Claim 4 (depends on 1)

The array base plate according to claim 1, wherein the array base plate further comprises a gate, a first gate insulating layer, and a second gate insulating layer, the gate is disposed on the substrate, the first gate insulating layer is disposed on the substrate and the gate, the second gate insulating layer is disposed on the first gate insulating layer, and the active layer is disposed on the second gate insulating layer, and is located above the gate.

### Claim 5 (depends on 4)

The array base plate according to claim 4, wherein the array base plate further comprises a first protective layer, a second protective layer, a passivation layer, and a pixel electrode; the first protective layer is disposed on the etching protective layer, the source, the drain, and the second gate insulating layer; the second protective layer, the passivation layer, and the pixel electrode are sequentially disposed on the first protective layer in a stacked manner; and the pixel electrode is connected to the drain.

### Claim 6 (depends on 1)

A display panel, comprising an array base plate according to claim 1.