# US 12,224,283 B2 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,283 B2 - Document ID: US12224283B2 - Status: Granted - Kind: B2 - Application number: 18/239,720 - Filed: 2023-08-29 - Published: 2023-12-21 - Granted: 2025-02-11 - Earliest claimed: 2021-07-23 - Assignees: Fujian Jinhua Integrated Circuit Co., Ltd. - Applicants: Fujian Jinhua Integrated Circuit Co., Ltd. - Inventors: Janbo Zhang; Yu-Cheng Tung - Web page: https://patentgrep.com/patent/US12224283B2 ## CPC - H10B 12/488: {Word lines} - H10D 84/83: of only insulated-gate FETs [IGFET] - H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells} - H10B 12/34: {the transistor being at least partially in a trench in the substrate} - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor memory device includes a substrate, an active structure, a shallow trench isolation and a plurality of word lines. The active structure is disposed in the substrate, and includes a plurality of first active fragments and a plurality of second active fragments extended parallel to each other along a first direction and the second active fragments are disposed outside a periphery of all of the first active fragments. The shallow trench isolation is disposed in the substrate to surround the active structure, and which includes a plurality of first portions and a plurality of second portions. The word lines are disposed in the substrate, parallel with each other to extend along a second direction, wherein at least one of the word lines are only intersected with the second active fragments, or at least one of the word lines does not pass through any one of the second portions. ## Claims ### Claim 1 A semiconductor memory device, comprising; a substrate; an active structure disposed in the substrate, the active structure comprising a plurality of first active fragments and a plurality of second active fragments, each of the plurality of first active fragments and each of the plurality of second active fragments extending parallel to each other along a first direction, the plurality of second active fragments being disposed outside a periphery of all of the plurality of first active fragments, wherein a length of each of the plurality of first active fragments in the first direction is different from a length of each of the plurality of second active fragments in the first direction; a shallow trench isolation, disposed in the substrate to surround the active structure; and a plurality of word lines, disposed in the substrate, the plurality of word lines being parallel with each other to extend along a second direction, at least one of the plurality of word lines being only intersected with the plurality of second active fragments, and the second direction being not perpendicular to the first direction. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein each of the plurality of first active fragments comprises a first length in the first direction, each of the plurality of second active fragments comprises a length greater or less than the first length. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein the plurality of first active fragments and the plurality of second active fragments comprise first gaps therebetween in the second direction, and the plurality of first active fragments and the plurality of second active fragments comprise second gaps therebetween in the first direction, the second gap is greater than the first gap, and the shallow trench isolation comprises a plurality of first portions and a plurality of second portions filled in the first gaps and the second gaps respectively. ### Claim 4 (depends on 3) The semiconductor memory device according to claim 3, wherein the at least one of the plurality of word lines does not intersect with any one of the second portions. ### Claim 5 (depends on 4) The semiconductor memory device according to claim 4, wherein others of the plurality of word lines intersect with the plurality of first portions and the plurality of second portions sequentially. ### Claim 6 (depends on 1) The semiconductor memory device according to claim 1, wherein the active structure comprises an active area surrounded the plurality of first active fragments and the plurality of second active fragments, and all of the plurality of second active fragments directly contact the active area. ### Claim 7 (depends on 6) The semiconductor memory device according to claim 6, wherein the active area comprises a plurality of segments, and each of the plurality of second active fragments directly contacts each of the plurality of segments. ### Claim 8 (depends on 6) The semiconductor memory device according to claim 6, wherein the active area comprises a plurality of segments, and any two adjacent ones of the plurality of second active fragments directly contact each of the plurality of segments. ### Claim 9 A semiconductor memory device, comprising; a substrate; an active structure disposed in the substrate, the active structure comprising a plurality of first active fragments and a plurality of second active fragments, each of the plurality of first active fragments and each of the plurality of second active fragments extending parallel to each other along a first direction, the plurality of second active fragments being disposed outside a periphery of all of the plurality of first active fragments, wherein a length of each of the plurality of first active fragments in the first direction is different from a length of each of the plurality of second active fragments in the first direction; a shallow trench isolation, disposed in the substrate to surround the active structure; and a plurality of word lines, disposed in the substrate, the plurality of word lines being parallel with each other to extend along a second direction, one of the plurality of word lines being intersected with at least three of the plurality of second active fragments which are arranged continuously in a sequence. ### Claim 10 (depends on 9) The semiconductor memory device according to claim 9, wherein each of the plurality of first active fragments comprises a first length in the first direction, each of the plurality of second active fragments comprises a length greater or less than the first length. ### Claim 11 (depends on 9) The semiconductor memory device according to claim 9, wherein the plurality of first active fragments and the plurality of second active fragments comprise first gaps therebetween in the second direction, and the plurality of first active fragments and the plurality of second active fragments comprise second gaps therebetween in the first direction, the second gap is greater than the first gap, and the shallow trench isolation comprises a plurality of first portions and a plurality of second portions filled in the first gaps and the second gaps respectively. ### Claim 12 (depends on 11) The semiconductor memory device according to claim 11, wherein the at least one of the plurality of word lines does not intersect with any one of the second portions. ### Claim 13 (depends on 12) The semiconductor memory device according to claim 12, wherein others of the plurality of word lines intersect with the plurality of first portions and the plurality of second portions sequentially. ### Claim 14 (depends on 9) The semiconductor memory device according to claim 9, wherein the active structure comprises an active area surrounded the plurality of first active fragments and the plurality of second active fragments, and all of the plurality of second active fragments directly contact the active area. ### Claim 15 (depends on 14) The semiconductor memory device according to claim 14, wherein the active area comprises a plurality of segments, and each of the plurality of second active fragments directly contacts each of the plurality of segments. ### Claim 16 (depends on 14) The semiconductor memory device according to claim 14, wherein the active area comprises a plurality of segments, and any two adjacent ones of the plurality of second active fragments directly contact each of the plurality of segments. ### Claim 17 A semiconductor memory device, comprising; a substrate; an active structure disposed in the substrate, the active structure comprising a plurality of first active fragments and a plurality of second active fragments, each of the plurality of first active fragments and each of the plurality of second active fragments extending parallel to each other along a first direction, the plurality of second active fragments being disposed outside a periphery of all of the plurality of first active fragments, wherein a length of each of the plurality of first active fragments in the first direction is different from a length of each of the plurality of second active fragments in the first direction; a shallow trench isolation, disposed in the substrate to surround the active structure; and a plurality of word lines, disposed in the substrate, the plurality of word lines being parallel with each other to extend along a second direction, wherein a distance between two ends of one of the plurality of second active fragments in a third direction is greater than a minimum distance from the one of the plurality of second active fragments to a closed one of the plurality of word lines. ### Claim 18 (depends on 17) The semiconductor memory device according to claim 17, wherein the plurality of first active fragments and the plurality of second active fragments comprise first gaps therebetween in the second direction, and the plurality of first active fragments and the plurality of second active fragments comprise second gaps therebetween in the first direction, the second gap is greater than the first gap, and the shallow trench isolation comprises a plurality of first portions and a plurality of second portions filled in the first gaps and the second gaps respectively. ### Claim 19 (depends on 18) The semiconductor memory device according to claim 18, wherein the closed one of the plurality of word lines does not intersect with any one of the second portions and others of the plurality of word lines intersect with the plurality of first portions and the plurality of second portions sequentially. ### Claim 20 (depends on 17) The semiconductor memory device according to claim 17, wherein the active structure comprises an active area surrounded the plurality of first active fragments and the plurality of second active fragments, and all of the plurality of second active fragments directly contact the active area.