# US 12,224,280 B2 · Electrostatic discharge protection circuit including a pulse detection circuit

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- Number: US 12,224,280 B2
- Document ID: US12224280B2
- Status: Granted
- Kind: B2
- Application number: 17/376,112
- Filed: 2021-07-14
- Published: 2021-11-04
- Granted: 2025-02-11
- Earliest claimed: 2020-03-26
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Qian Xu
- Web page: https://patentgrep.com/patent/US12224280B2

## CPC

- H10D 89/811: {using FETs as protective elements}
- H02H 3/046: {Signalling the blowing of a fuse (detecting non functioning of a lamp H05B47/20)}
- H02H 9/045: {adapted to a particular application and not provided for elsewhere}
- H03K 17/08104: {in field-effect transistor switches (H03K17/0812, H03K17/0814 take precedence)}
- H10D 89/819: {Bias arrangements for gate electrodes of FETs, e.g. RC networks or voltage partitioning circuits (FETs in a Darlington configuration H10D89/817)}
- H10D 89/911: {using passive elements as protective elements}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An electrostatic discharge protection circuit includes: a pulse detection unit, a delay unit, a control unit, and a discharge unit. The pulse detection unit is configured to detect an electrostatic pulse signal; the delay unit is configured to delay or enhance driving capability of the pulse detection signal output by the pulse detection unit; the control unit is configured to generate a control signal based on a first delay signal and a second delay signal output by the delay unit; and the discharge unit is configured to open or close an electrostatic charge discharge passage based on the control signal output by the control unit.

## Claims

### Claim 1

An electrostatic discharge protection circuit, comprising:
a pulse detection circuit, configured to detect an electrostatic pulse signal, the pulse detection circuit having a first end connected to a first voltage, a second end connected to a second voltage, and a third end configured to output a pulse detection signal;
a delay circuit, configured to delay or enhance driving capability of the pulse detection signal, the delay circuit having a first end connected to the first voltage, a second end connected to the second voltage, a third end connected to the third end of the pulse detection circuit, a fourth end configured to output a first delay signal, and a fifth end configured to output a second delay signal;
a control circuit, configured to generate a control signal based on the first delay signal and the second delay signal, the control circuit having a first end connected to the first voltage, a second end connected to the second voltage, a third end connected to the fifth end of the delay circuit, a fourth end connected to the fourth end of the delay circuit, and a fifth end configured to output the control signal; and
a discharge circuit, configured to open or close an electrostatic charge discharge passage based on the control signal, the discharge circuit having a first end connected to the first voltage, a second end connected to the second voltage, and a third end connected to the fifth end of the control circuit;
wherein the delay circuit comprises:
a first inverter having a first end used as the third end of the delay circuit, a second end connected to the first voltage, a third end connected to the second voltage, and a fourth end used as the fourth end of the delay circuit; and
a second inverter having a first end connected to the fourth end of the first inverter, a second end connected to the first voltage, a third end connected to the second voltage, and a fourth end used as the fifth end of the delay circuit;
wherein the control circuit comprises:
a third PMOS transistor, a source of the third PMOS transistor being connected to the first voltage;
a third NMOS transistor, a gate of the third NMOS transistor being connected to the fourth end of the first inverter, a drain of the third NMOS transistor being connected to a drain of the third PMOS transistor, and a source of the third NMOS transistor being connected to the second voltage;
a fourth PMOS transistor, a gate of the fourth PMOS transistor being connected to the drain of the third PMOS transistor and the drain of the third NMOS transistor, and a source of the fourth PMOS transistor being connected to the first voltage; and
a fourth NMOS transistor, a gate of the fourth NMOS transistor being connected to the fourth end of the second inverter, a drain of the fourth NMOS transistor being connected to a drain of the fourth PMOS transistor and a gate of the third PMOS transistor and used as the fifth end of the control circuit.

### Claim 2 (depends on 1)

The electrostatic discharge protection circuit of claim 1, wherein
the first inverter comprises a first P-channel Metal-Oxide-Semiconductor (PMOS) transistor and a first N-channel MOS (NMOS) transistor; a gate of the first PMOS transistor and a gate of the first NMOS transistor are connected together and used as the first end of the first inverter; a source of the first PMOS transistor is used as the second end of the first inverter; a drain of the first PMOS transistor and a drain of the first NMOS transistor are connected together and used as the fourth end of the first inverter; and a source of the first NMOS transistor is used as the third end of the first inverter; and
the second inverter comprises a second PMOS transistor and a second NMOS transistor;
a gate of the second PMOS transistor and a gate of the second NMOS transistor are connected together and used as the first end of the second inverter; a source of the second PMOS transistor is used as the second end of the second inverter; a drain of the second PMOS transistor and a drain of the second NMOS transistor are connected together and used as the fourth end of the second inverter; and a source of the second NMOS transistor is used as the third end of the second inverter.

### Claim 3 (depends on 1)

The electrostatic discharge protection circuit of claim 1, wherein the pulse detection circuit comprises a resistor and a capacitor, and
the resistor has a first end used as the first end of the pulse detection circuit, and a second end used as the third end of the pulse detection circuit; the capacitor has a first end connected to the second end of the resistor, and a second end used as the second end of the pulse detection circuit.

### Claim 4 (depends on 3)

The electrostatic discharge protection circuit of claim 3, wherein the resistor is a polysilicon resistor or a doped resistor.

### Claim 5 (depends on 3)

The electrostatic discharge protection circuit of claim 3, wherein the capacitor is a metal-dielectric layer-metal capacitor or a Metal-Oxide-Semiconductor (MOS) capacitor.

### Claim 6 (depends on 3)

The electrostatic discharge protection circuit of claim 3, wherein a product of resistance of the resistor and capacitance of the capacitor has a value from 0.01 us to 1 us.

### Claim 7 (depends on 1)

The electrostatic discharge protection circuit of claim 1, wherein the discharge circuit comprises a discharge transistor.

### Claim 8 (depends on 7)

The electrostatic discharge protection circuit of claim 7, wherein the discharge transistor comprises an NMOS transistor; a gate of the discharge transistor is used as the third end of the discharge circuit; a drain of the discharge transistor is used as the first end of the discharge circuit; and a source of the discharge transistor is used as the second end of the discharge circuit.