# US 12,224,279 B2 · Integrated mult-device chip and package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,279 B2 - Document ID: US12224279B2 - Status: Granted - Kind: B2 - Application number: 17/615,927 - Filed: 2019-06-03 - Published: 2022-10-06 - Granted: 2025-02-11 - Earliest claimed: 2019-06-03 - Assignees: Littelfuse Semiconductor (Wuxi) Co., Ltd. - Applicants: Littelfuse Semiconductor (Wuxi) Co., Ltd. - Inventors: Tsung-Wen Mou; Lei Shi; Jifeng Zhou - Web page: https://patentgrep.com/patent/US12224279B2 ## CPC - H10D 18/00: Thyristors - H10D 89/711: {using bipolar transistors as protective elements} - H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 89/611: {using diodes as protective elements} - H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices} - H10W 70/421: {Shapes or dispositions} - H10W 70/466: {Tape carriers or flat leads} - H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00} - H10W 90/00: Package configurations - H10D 89/921: {characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses} - H10W 42/80: protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) - H10W 74/114: {by a substrate and the encapsulations} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A protection device may include a semiconductor substrate and a thyristor-type device, formed within the semiconductor substrate, where the thyristor device extends from a first main surface of the semiconductor substrate to a second main surface of the semiconductor substrate. The protection device may include a first PN diode, formed within the semiconductor substrate; and a second PN diode, formed within the semiconductor substrate, wherein the thyristor-type device is arranged in electrical series between the first PN diode and the second PN diode. ## Claims ### Claim 1 A protection device, comprising: a semiconductor substrate; a thyristor-type device, formed within the semiconductor substrate, the thyristor-type device extending from a first main surface of the semiconductor substrate to a second main surface of the semiconductor substrate; a first PN diode, formed within the semiconductor substrate; a second PN diode, formed within the semiconductor substrate, wherein the thyristor-type device is arranged in electrical series between the first PN diode and the second PN diode; and an electrical isolation barrier, extending from the first main surface to the second main surface, and disposed between the second PN diode and the thyristor-type device. ### Claim 2 (depends on 1) The protection device of claim 1, wherein the second PN diode extends from the first main surface to the second main surface. ### Claim 3 (depends on 1) The protection device of claim 1, wherein the first PN diode extends from the second main surface and forms a portion of the thyristor-type device. ### Claim 4 (depends on 1) The protection device of claim 1, further comprising a front surface metal layer, disposed on the first main surface and disposed in contact with the thyristor-type device and the second PN diode. ### Claim 5 (depends on 1) The protection device of claim 1, wherein the second main surface comprises: a first plurality of P-type regions, electrically isolated from one another; and a second plurality of N-type regions, electrically isolated from one another, and equal in number to the first plurality of P-type regions. ### Claim 6 A protection device assembly, comprising: a semiconductor substrate having a first main surface and a second main surface, and comprising: a thyristor-type device, extending from a first main surface to the second main surface; a first PN diode, extending from the second main surface; and a second PN diode, wherein the thyristor-type device is arranged in electrical series between the first PN diode and the second PN diode; a front surface metal layer, disposed on the first main surface; a leadframe, disposed in contact with the second main surface; and an electrical isolation barrier, extending from the first main surface to the second main surface, and disposed between the second PN diode and the thyristor-type device. ### Claim 7 (depends on 6) The protection device assembly of claim 6, the leadframe comprising: a plurality of leads, disposed in contact with the second main surface. ### Claim 8 (depends on 7) The protection device assembly of claim 7, the second main surface comprising: a first plurality of P-type regions, electrically isolated from one another; and a first plurality of N-type regions, electrically isolated from one another, and equal in number to the first plurality of P-type regions, wherein the first plurality of P-type regions are elongated along a first direction, wherein the plurality of leads extend along the first direction, in contact with the first plurality of P-type regions and the first plurality of N-type regions. ### Claim 9 (depends on 7) The protection device assembly of claim 7, further comprising an insulating housing, extending around the semiconductor substrate and between adjacent leads of the plurality of leads. ### Claim 10 (depends on 6) The protection device assembly of claim 6, wherein the leadframe comprises four leads. ### Claim 11 (depends on 6) The protection device assembly of claim 6, wherein the second PN diode extends from the first main surface to the second main surface. ### Claim 12 A line protection device, comprising: a semiconductor substrate having a first main surface and a second main surface, the semiconductor substrate comprising; a thyristor-type device, extending from a first main surface to the second main surface; a first PN diode, extending from the second main surface; a second PN diode, wherein the thyristor-type device is arranged in electrical series between the first PN diode and the second PN diode; and an electrical isolation barrier, extending from the first main surface to the second main surface, and disposed between the second PN diode and the thyristor-type device; a front surface metal layer, disposed on the first main surface; and a leadframe, disposed in contact with the second main surface, the leadframe comprising a plurality of leads, arranged electrically in parallel to one another. ### Claim 13 (depends on 12) The line protection device of claim 12, the second main surface comprising: a first plurality of P-type regions, electrically isolated from one another; and a first plurality of N-type regions, electrically isolated from one another, and equal in number to the first plurality of P-type regions, wherein the first plurality of P-type regions are elongated along a first direction, wherein the plurality of leads extend along the first direction, in contact with the first plurality of P-type regions and the first plurality of N-type regions. ### Claim 14 (depends on 12) The line protection device of claim 12, wherein the leadframe comprises four leads. ### Claim 15 (depends on 12) The line protection device of claim 12, wherein the second PN diode extends from the first main surface to the second main surface. ### Claim 16 (depends on 12) The line protection device of claim 12, the semiconductor substrate further comprising an electrical isolation barrier, extending from the first main surface to the second main surface, and disposed between the second PN diode and the thyristor-type device. ### Claim 17 (depends on 12) The line protection device of claim 12, further comprising an insulating housing, extending around the semiconductor substrate and between adjacent leads of the plurality of leads.