# US 12,224,277 B2 · Memory devices having cell over periphery structure, memory packages including the same, and methods of manufacturing the same

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- Number: US 12,224,277 B2
- Document ID: US12224277B2
- Status: Granted
- Kind: B2
- Application number: 18/149,206
- Filed: 2023-01-03
- Published: 2023-05-11
- Granted: 2025-02-11
- Earliest claimed: 2019-12-27
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yonghyuk Choi; Bongsoon Lim; Hongsoo Jeon; Jaeduk Yu
- Web page: https://patentgrep.com/patent/US12224277B2

## CPC

- H10W 90/00: Package configurations
- G11C 8/14: Word line organisation; Word line lay-out
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- H10B 43/40: characterised by the peripheral circuit region
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 72/0198: {batch processes}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.

## Claims

### Claim 1

A memory device, comprising:
a first semiconductor layer including a plurality of wordlines extending in a first direction and a plurality of bitlines extending in a second direction that is perpendicular to the first direction, the first semiconductor layer further including
an upper substrate, and
a memory cell array on the upper substrate and including a first memory block; and
a second semiconductor layer beneath the first semiconductor layer in a third direction, the third direction perpendicular to both the first direction and the second direction, the second semiconductor layer including
a lower substrate, and
an address decoder on the lower substrate and configured to control the memory cell array,
wherein the first memory block includes
a first core region including first memory cells, and
a first extension region adjacent to a first side of the first core region, the first extension region including an insulating mold structure,
wherein the first extension region includes
a plurality of step zones having a step shape in a cross-sectional view, and
at least one flat zone having a flat shape in the cross-sectional view,
wherein the memory device further includes a plurality of through-hole vias penetrating the insulating mold structure in the at least one flat zone,
wherein the plurality of wordlines and the address decoder are electrically connected to each other by at least the plurality of through-hole vias, and
wherein a quantity of step zones in the first extension region is equal to a quantity of flat zones in the first extension region.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein:
the plurality of step zones include a first step zone and a second step zone that extend sequentially in a first series pattern along the first direction,
the at least one flat zone includes a first flat zone and a second flat zone that extend sequentially in a second series pattern along the first direction,
the first flat zone is between the first step zone and the second step zone, and
the second step zone is between the first flat zone and the second flat zone.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein:
the memory cell array further includes a second memory block,
the first memory block and the second memory block extend sequentially in a serial pattern along the second direction, and
the second memory block includes
a second core region including second memory cells, and
a second extension region adjacent to a first side of the second core region, the second extension region including a plurality of wordline contacts configured to establish an electrical connection with the plurality of wordlines.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein:
the second extension region includes
a first wordline step zone and a second wordline step zone that extend sequentially in the first series pattern along the first direction, and
a first wordline flat zone and a second wordline flat zone that extend sequentially in the second series pattern along the first direction,
the first wordline flat zone is between the first wordline step zone and the second wordline step zone, and
the second wordline step zone is between the first wordline flat zone and the second wordline flat zone.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein:
the plurality of wordline contacts include first wordline contacts in the first wordline step zone and second wordline contacts in the second wordline step zone,
the plurality of through-hole vias include first through-hole vias in the first flat zone and second through-hole vias in the second flat zone,
the first wordline contacts are connected to the first through-hole vias, and
the second wordline contacts are connected to the second through-hole vias.

### Claim 6 (depends on 4)

The memory device of claim 4, wherein:
the first step zone and the first wordline step zone are aligned along the second direction,
the second step zone and the second wordline step zone are aligned along the second direction,
the first flat zone and the first wordline flat zone are aligned along the second direction, and
the second flat zone and the second wordline flat zone are aligned along the second direction.

### Claim 7 (depends on 2)

The memory device of claim 2, wherein, among the plurality of through-hole vias, a first quantity of through-hole vias in the first flat zone is equal to a second quantity of through-hole vias in the second flat zone.

### Claim 8 (depends on 7)

The memory device of claim 7, wherein:
a size of the first flat zone is equal to a size of the second flat zone, and
a size of the first step zone is equal to a size of the second step zone.

### Claim 9 (depends on 2)

The memory device of claim 2, wherein, among the plurality of through-hole vias, a first quantity of through-hole vias in the first flat zone is different from a second quantity of through-hole vias in the second flat zone.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein:
a size of the first flat zone is greater than a size of the second flat zone, and
the first quantity is greater than the second quantity.

### Claim 11 (depends on 9)

The memory device of claim 9, wherein:
a size of the first step zone is greater than a size of the second step zone, and
the first quantity is greater than the second quantity.

### Claim 12

A memory device, comprising:
a first semiconductor layer including a plurality of wordlines extending in a first direction and a plurality of bitlines extending in a second direction that is perpendicular to the first direction, the first semiconductor layer further including
an upper substrate, and
a memory cell array on the upper substrate and including a first memory block; and
a second semiconductor layer beneath the first semiconductor layer in a third direction, the third direction perpendicular to both the first direction and the second direction, the second semiconductor layer including
a lower substrate, and
an address decoder on the lower substrate and configured to control the memory cell array,
wherein the first memory block includes
a first core region including first memory cells, and
a first extension region adjacent to a first side of the first core region, the first extension region including an insulating mold structure,
wherein the first extension region includes
a plurality of step zones having a step shape in a cross-sectional view, and
at least one flat zone having a flat shape in the cross-sectional view,
wherein the memory device further includes a plurality of through-hole vias penetrating the insulating mold structure in the at least one flat zone,
wherein the plurality of wordlines and the address decoder are electrically connected to each other by at least the plurality of through-hole vias, and
wherein a quantity of step zones in the first extension region is greater than a quantity of flat zones in the first extension region.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein:
the plurality of step zones include a first step zone and a second step zone that extend sequentially in a first series pattern along the first direction, and
the at least one flat zone includes a first flat zone between the first step zone and the second step zone.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein:
the memory cell array further includes a second memory block,
the first memory block and the second memory block extend sequentially in a serial pattern along the second direction, and
the second memory block includes
a second core region including second memory cells, and
a second extension region adjacent to a first side of the second core region, the second extension region including a plurality of wordline contacts configured to establish an electrical connection with the plurality of wordlines.

### Claim 15 (depends on 14)

The memory device of claim 14, wherein:
the second extension region includes
a first wordline step zone and a second wordline step zone that extend sequentially in the first series pattern along the first direction, and
a first wordline flat zone between the first wordline step zone and the second wordline step zone.

### Claim 16 (depends on 15)

The memory device of claim 15, wherein:
the plurality of wordline contacts include first wordline contacts in the first wordline step zone and second wordline contacts in the second wordline step zone,
the plurality of through-hole vias include first through-hole vias in the first flat zone, and
the first wordline contacts and the second wordline contacts are connected to the first through-hole vias.

### Claim 17 (depends on 15)

The memory device of claim 15, wherein:
the first step zone and the first wordline step zone are aligned along the second direction,
the second step zone and the second wordline step zone are aligned along the second direction, and
the first flat zone and the first wordline flat zone are aligned along the second direction.

### Claim 18

A method of manufacturing a memory device including a first semiconductor layer and a second semiconductor layer that are stacked in a third direction perpendicular to first and second directions crossing each other, the method comprising:
forming the second semiconductor layer that includes a lower substrate and an address decoder on the lower substrate, the address decoder configured to control a memory cell array; and
forming the first semiconductor layer stacked on the second semiconductor layer in the third direction, the first semiconductor layer including an upper substrate and the memory cell array on the upper substrate, the memory cell array including a plurality of memory blocks extending sequentially in a serial pattern, a plurality of wordlines extending in a first direction, and a plurality of bitlines extending in a second direction crossing the first direction,
wherein each memory block of the plurality of memory blocks includes
a core region including a plurality of memory cells,
a first extension region formed adjacent to a first side of the core region, and
a second extension region formed adjacent to a second side of the core region opposite the first side,
wherein forming the first semiconductor layer includes
forming a mold structure based on repeatedly stacking insulating interlayers and sacrificial layers on the upper substrate alternately along the third direction,
forming the first extension region and the second extension region based on partially removing the mold structure,
forming wordline cut regions, the wordline cut regions being formed along a boundary of the core region and a boundary of the first extension region, the wordline cut regions being formed to cross an inner portion of the core region and an inner portion of the first extension region, the wordline cut regions being not formed in the second extension region,
removing the sacrificial layers in the core region and in the first extension region using the wordline cut regions to form one or more spaces,
forming the plurality of wordlines in the one or more spaces,
forming a plurality of wordline contacts configured to establish an electrical connection with the plurality of wordlines in the first extension region,
forming a plurality of through-hole vias in the second extension region, and
electrically connecting the plurality of wordline contacts with separate, respective through-hole vias of the plurality of through-hole vias,
wherein the second extension region includes
a plurality of step zones having a step shape in a cross-sectional view, and
at least one flat zone having a flat shape in the cross-sectional view,
wherein the plurality of through-hole vias are formed in the at least one flat zone, and
wherein the plurality of wordlines and the address decoder are electrically connected with each other by at least the plurality of through-hole vias.

### Claim 19 (depends on 18)

The method of claim 18, wherein:
in the first extension region, the plurality of wordlines and the insulating interlayers extend in parallel to each other in an alternating pattern in the third direction, and
in the second extension region, the sacrificial layers and the insulating interlayers extend in parallel to each other in a separate alternating pattern in the third direction.

### Claim 20 (depends on 19)

The method of claim 19, wherein:
the plurality of wordlines include a conductive material,
the insulating interlayers include a silicon oxide based material, and
the sacrificial layers include a silicon nitride based material.