# US 12,224,276 B2 · 3D semiconductor packages

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- Number: US 12,224,276 B2
- Document ID: US12224276B2
- Status: Granted
- Kind: B2
- Application number: 17/837,039
- Filed: 2022-06-10
- Published: 2022-09-22
- Granted: 2025-02-11
- Earliest claimed: 2019-08-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chen-Hua Yu; Chun-Hui Yu; Kuo-Chung Yee; Liang-Ju Yen
- Web page: https://patentgrep.com/patent/US12224276B2

## CPC

- H10W 40/778: {in encapsulations}
- H10W 90/00: Package configurations
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 72/7448: {the bond interface between the auxiliary support and the wafer comprising two or more, e.g. multilayer adhesive or adhesive and release layer}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/095: {of vias therein}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/685: comprising multiple insulating layers
- H10W 74/014: {using batch processing}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/853: {On the same surface}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/733: {between laterally-adjacent chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a first die, a first heat conduction block and a first encapsulant. The first die has a bottom surface, a top surface and a sidewall between the bottom surface and the top surface. The first heat conduction block has a bottom surface, a top surface and a sidewall between the bottom surface and the top surface. The first encapsulant is disposed between the sidewall of the first die and the sidewall of the first heat conduction block.

## Claims

### Claim 1

A semiconductor package, comprising:
a first die having a bottom surface, a top surface and a sidewall between the bottom surface and the top surface;
a silicon block having a bottom surface, a top surface and a sidewall between the bottom surface and the top surface;
a first encapsulant, disposed between the sidewall of the first die and the sidewall of the silicon block, wherein the top surface of the silicon block is coplanar with a top surface of the first encapsulant; and
an adhesive adhered to the bottom surface of the silicon block.

### Claim 2 (depends on 1)

The semiconductor package as claimed in claim 1 further comprising a second die and a second encapsulant encapsulating the second die and disposed below the first encapsulant.

### Claim 3 (depends on 2)

The semiconductor package as claimed in claim 2 further comprising a third die and a third encapsulant encapsulating the third die, wherein the second encapsulant is disposed between the first encapsulant and the third encapsulant.

### Claim 4 (depends on 1)

The semiconductor package as claimed in claim 1, wherein the silicon block is free of active device and passive device.

### Claim 5 (depends on 1)

The semiconductor package as claimed in claim 1, further comprising a heat conduction block, wherein the silicon block and the heat conduction block are disposed at opposite sides of the first die.

### Claim 6 (depends on 1)

The semiconductor package as claimed in claim 1, wherein the top surfaces of the first encapsulant and the silicon block are substantially coplanar with the top surface of the first die.

### Claim 7 (depends on 1)

The semiconductor package as claimed in claim 1, wherein a bottom surface of the adhesive is substantially coplanar with the bottom surface of the first die.

### Claim 8

A semiconductor package, comprising:
a first die having a bottom surface, a top surface and a sidewall between the bottom surface and the top surface;
at least one semiconductor block comprising a semiconductor material, extending along the sidewall of the first die, wherein the at least one semiconductor block is free of active device and passive device;
an encapsulant, wherein the encapsulant encapsulates opposite sidewalls of the at least one semiconductor block; and
an adhesive adhered to a bottom surface of the at least one semiconductor block.

### Claim 9 (depends on 8)

The semiconductor package as claimed in claim 8, wherein the at least one semiconductor block includes a plurality of semiconductor blocks, and the semiconductor blocks are disposed at opposite sides of the first die.

### Claim 10 (depends on 8)

The semiconductor package as claimed in claim 8, wherein the opposite sidewalls of the at least one semiconductor block are flush with opposite sidewalls of the adhesive.

### Claim 11 (depends on 8)

The semiconductor package as claimed in claim 8, wherein a top surface of the at least one semiconductor block is substantially coplanar with the top surface of the first die.

### Claim 12 (depends on 8)

The semiconductor package as claimed in claim 8, wherein the encapsulant further encapsulates the first die, and the encapsulant is in direct contact with the opposite sidewalls of the at least one semiconductor block.

### Claim 13 (depends on 8)

The semiconductor package as claimed in claim 8, further comprising a second die, a first redistribution layer structure, a second redistribution layer structure and a plurality of through vias, wherein the first redistribution layer structure is disposed between the first die and the second die, the second die is disposed between the first die and the second redistribution layer structure, and the through vias are disposed between the first redistribution layer structure and the second redistribution layer structure.

### Claim 14

A semiconductor package, comprising:
a first die;
a semiconductor block, disposed aside the first die, wherein the at least one semiconductor block is free of active device and passive device; and
a heat conduction block, adhered to the semiconductor block through an adhesive.

### Claim 15 (depends on 14)

The semiconductor package as claimed in claim 14, wherein the heat conduction block includes a semiconductor material, a conductive material or a combination thereof.

### Claim 16 (depends on 14)

The semiconductor package as claimed in claim 14, further comprising a dielectric layer between the semiconductor block and the adhesive.

### Claim 17 (depends on 14)

The semiconductor package as claimed in claim 14, further comprising a second die, wherein the heat conduction block is disposed aside the second die below the first die and the semiconductor block.

### Claim 18 (depends on 14)

The semiconductor package as claimed in claim 14, wherein the semiconductor block and the first die are encapsulated by a first encapsulant, and the heat conduction block is encapsulated by a second encapsulant.

### Claim 19 (depends on 14)

The semiconductor package as claimed in claim 14, wherein a surface of the first die is substantially coplanar with a surface of the semiconductor block.

### Claim 20 (depends on 14)

The semiconductor package as claimed in claim 14, wherein a sidewall of the adhesive is substantially flush with one of sidewalls of the semiconductor block and the heat conduction block.