# US 12,224,275 B2 · TSV check circuit with replica path

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,224,275 B2
- Document ID: US12224275B2
- Status: Granted
- Kind: B2
- Application number: 17/489,502
- Filed: 2021-09-29
- Published: 2022-01-27
- Granted: 2025-02-11
- Earliest claimed: 2019-09-19
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Harutaka Makabe
- Web page: https://patentgrep.com/patent/US12224275B2

## CPC

- G11C 29/025: {in signal lines}
- H10W 90/00: Package configurations
- G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 7/227: {Timing of memory operations based on dummy memory elements or replica circuits}
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 29/12015: {comprising clock generation or timing circuitry}
- G11C 29/24: Accessing extra cells, e.g. dummy cells or redundant cells
- G11C 29/50012: {of timing}
- G11C 29/702: {by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones}
- H10P 74/232: {comprising connection or disconnection of parts of a device in response to a measurement}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 8/10: Decoders
- G11C 2029/0407: {on power on}
- G11C 2207/005: Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
- H10W 72/07254: {changes in dispositions}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path.

## Claims

### Claim 1

A method comprising:
charging a first path and a second path with a first voltage;
comparing potentials of the first path and the second path after charging;
activating, responsive to the potential of the first path being lower than the potential of the second path, an output signal at a low level; and
replacing the first path with the second path responsive to the output signal being at the low level.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
activating a fail signal responsive to the output signal being at the low level.

### Claim 3

A method comprising:
charging a first path and a second path with a first voltage;
comparing potentials of the first path and the second path after charging;
activating, responsive to the potential of the first path being lower than the potential of the second path, an output signal at a low level;
replacing the first path with the second path; and
charging the first and second paths simultaneously with the first voltage.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
discharging the first and second paths simultaneously during a first period of an activation period of a selection signal; and
charging the first and second path simultaneously in a second period subsequent to the first period.

### Claim 5 (depends on 4)

The method of claim 4, wherein comparing the potentials of the first and second paths take place during the second period.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
providing an enable signal to the second signal path; and
activating the enable signal during a test period.

### Claim 7 (depends on 1)

The method of claim 1, wherein replacing the first path with the second path comprises using the second path in place of the first path.

### Claim 8

An apparatus comprising:
a first signal path including a first TSV;
a first node coupled to the first signal path;
a second signal path including a second TSV;
a second node coupled to the second signal path; and
a comparator configured to compare a level at the first node coupled to the first signal path and a level at the second node coupled to the second signal path in response to a comparison signal.

### Claim 9 (depends on 8)

The apparatus of claim 8,
wherein the first signal path comprises a first transistor configured to receive a selection signal,
wherein the first node is coupled to the first signal path via the first transistor,
wherein the second signal path comprises a second transistor configured to receive an enable signal and a resistor inserted in series, and
wherein the second node is coupled to the second signal path via the second transistor.

### Claim 10

An apparatus comprising:
a first signal path including a first TSV;
a first node coupled to the first signal path;
a second signal path including a second TSV;
a second node coupled to the second signal path; and
a comparator configured to compare a level at the first node and a level at the second node with each other in response to a comparison signal, wherein the comparator is configured to place an output signal at a low level responsive to the level at the first node being lower than the level at the second node, wherein a fail signal is activated, and wherein the first signal path is replaced with the second signal path responsive to the activation of the fail signal.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the comparator is configured to place an output signal at a high level responsive to the level at the first node being higher than the level at the second node.

### Claim 12

An apparatus comprising:
a first signal path including a first TSV;
a first node coupled to the first signal path;
a second signal path including a second TSV;
a second node coupled to the second signal path; and
a comparator configured to compare a level at the first node and a level at the second node with each other in response to a comparison signal, wherein the first signal path includes a first parasitic capacitance and the second signal path includes a second parasitic capacitance, wherein the first parasitic capacitance and the second capacitance have the same value.

### Claim 13 (depends on 8)

The apparatus of claim 8, wherein the comparison signal is activated at a timing after a test clock signal provided to each of the first signal path and the second signal path is changed from a first level to a second level and before the test clock signal is changed from the second level to the first level.

### Claim 14 (depends on 9)

The apparatus of claim 9, wherein the resistor comprises a plurality of resistors connected in parallel.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein each resistor of the plurality of resistors is configured to turn on a respective transistor by using a respective selection signal.

### Claim 16 (depends on 14)

The apparatus of claim 14, wherein each resistor of the plurality of resistors has a different resistance value from one another.

### Claim 17

An apparatus comprising:
a first signal path including a first TSV and a first transistor, the first transistor configured to receive a selection signal;
a first node coupled to the first signal path;
a second signal path including a second TSV and a second transistor, the second transistor configured to receive an enable signal;
a second node coupled to the second signal path; and
a comparator configured to:
compare a level at the first node and a level at the second node with each other;
place an output signal at a low level if the level at the second node is higher than the level at the first node; and
activate a fail signal in response to the output signal being at the low level.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the second signal path further includes a third TSV connected in parallel with the second TSV, and wherein a resistance value of the second signal path is lower than a resistance value of the first signal path.

### Claim 19 (depends on 17)

The apparatus of claim 17, wherein the second signal path further comprises a plurality of resistors connected in parallel and a series of transistors connected in series to respective resistors of the plurality of resistors, wherein each of the transistor of the series of transistors is tuned on by a respective selection signal.

### Claim 20 (depends on 17)

The apparatus of claim 17, wherein the first path further comprises a first capacitance and the second path further comprises a second capacitance and a third capacitance, wherein the first capacitance and the second capacitance have same values as each other, and wherein a time constant of the second path is larger than a time constant of the first signal path.