# US 12,224,271 B2 · Integrating control circuits with light emissive circuits with dissimilar wafer sizes

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- Number: US 12,224,271 B2
- Document ID: US12224271B2
- Status: Granted
- Kind: B2
- Application number: 17/193,871
- Filed: 2021-03-05
- Published: 2021-09-16
- Granted: 2025-02-11
- Earliest claimed: 2020-03-10
- Assignees: Meta Platforms Technologies, LLC
- Applicants: Meta Platforms Technologies, LLC
- Inventors: Rajendra D. Pendse
- Web page: https://patentgrep.com/patent/US12224271B2

## CPC

- H10W 90/00: Package configurations
- G02B 27/0081: {with means for altering, e.g. enlarging, the entrance or exit pupil}
- G06F 1/163: {Wearable computers, e.g. on a belt}
- H10H 20/01: Manufacture or treatment
- H10H 20/013: {having light-emitting regions comprising only Group III-V materials}
- H10H 20/852: Encapsulations
- H10H 20/857: Interconnections, e.g. lead-frames, bond wires or solder balls
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 74/01: Manufacture or treatment
- H10W 74/014: {using batch processing}
- G02B 27/0172: {characterised by optical features}
- G02B 2027/0112: {comprising device for genereting colour display}
- H10H 20/0362: {of encapsulations}
- H10H 20/0364: {of interconnections}
- H10P 72/7428: {used to support diced chips prior to mounting}
- H10P 72/7434: {used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In some examples, an article comprises a semiconductor including at least one integrated circuit, a μLED array on a first surface of the semiconductor, and a fill material disposed on a first edge of the semiconductor. The first edge of the μLED array or the semiconductor is oriented substantially perpendicular to the first surface of the semiconductor.

## Claims

### Claim 1

An article comprising:
a first semiconductor including at least one integrated circuit;
a first μLED array on a first surface of the first semiconductor;
a fill material disposed on a first edge of the first semiconductor and extending in a direction substantially perpendicular to the first surface of the first semiconductor to be also disposed on a first edge of the first μLED array, wherein the first edge of the first μLED array and the first edge of the first semiconductor are substantially co-planar and are oriented substantially perpendicularly to the first surface of the first semiconductor; and
a second semiconductor including at least one integrated circuit, wherein the fill material joins the first and second semiconductors.

### Claim 2 (depends on 1)

The article of claim 1, the article further comprising:
a second μLED array on a first surface of the second semiconductor,
wherein the first and second μLED arrays are configured to emit light of a different color from each other.

### Claim 3 (depends on 2)

The article of claim 2, wherein at least one of the first and second μLED arrays are configured to emit at least one of red light, green light, or blue light.

### Claim 4 (depends on 2)

The article of claim 2, wherein respective light emitting surfaces of the first and second μLED arrays are substantially co-planar.

### Claim 5 (depends on 2)

The article of claim 2, further comprising:
a third semiconductor including at least one integrated circuit; and
a third μLED array on a first surface of the third semiconductor,
wherein the fill material joins the second and third semiconductors,
wherein the third μLED array is configured to emit light of a different color from the first and second μLED arrays, and
wherein each of the first, second, and third semiconductors include at least one through substrate via.

### Claim 6 (depends on 1)

The article of claim 1, wherein the fill material comprises an oxide or a dielectric polymer.

### Claim 7 (depends on 1)

The article of claim 1, wherein the first semiconductor includes at least one through substrate via.

### Claim 8 (depends on 1)

The article of claim 1, wherein the first μLED array is formed in an inorganic semiconductor layer.

### Claim 9 (depends on 8)

The article of claim 8, wherein the inorganic semiconductor layer comprises an epitaxial layer or at least one of gallium nitride, gallium arsenide, indium gallium nitride, or indium gallium arsenide.

### Claim 10 (depends on 1)

The article of claim 1, wherein the at least one integrated circuit of the first semiconductor comprises a CMOS device driver integrated circuit (DDIC) or a bi-CMOS DDIC.

### Claim 11

A method comprising:
attaching at least one semiconductor including at least one integrated circuit and a μLED array to a carrier wafer, wherein the carrier wafer has a diameter different than a diameter of the at least one semiconductor;
after attaching the at least one semiconductor to the carrier wafer, encapsulating the at least one semiconductor with a fill material;
forming at least one through substrate via in the at least one semiconductor, wherein the diameter of the carrier wafer is larger than the diameter of the at least one semiconductor; and
thinning and planarizing the at least one semiconductor and the fill material to a predetermined thickness, wherein the fill material comprises an oxide.

### Claim 12 (depends on 11)

The method of claim 11, wherein the μLED array comprises at least one of gallium nitride, gallium arsenide, indium gallium nitride, and indium gallium arsenide.

### Claim 13 (depends on 11)

The method of claim 11, wherein the at least one integrated circuit comprises a CMOS device driver integrated circuit (DDIC) or a bi-CMOS DDIC.

### Claim 14 (depends on 11)

The method of claim 11, wherein the predetermined thickness is about 150 microns.

### Claim 15 (depends on 11)

The method of claim 11, further comprising:
coating a thin protecting layer over exposed surfaces and/or sidewalls of the at least one semiconductor, the fill material, and the carrier wafer prior to forming the at least one through substrate via.

### Claim 16 (depends on 11)

The method of claim 11, wherein the diameter of the at least one semiconductor is 200 mm or less, and wherein the diameter of the carrier wafer is about 300 mm.

### Claim 17 (depends on 11)

The method of claim 11, wherein the at least one semiconductor comprises a first semiconductor including a first μLED array and a second semiconductor including a second μLED array, wherein the first and second μLED arrays are configured to emit light of a different color from each other in a final color arrangement.

### Claim 18 (depends on 17)

The method of claim 17, wherein respective light emitting surfaces of the first and second μLED arrays are configured to be co-planar upon attachment of the first and second semiconductors to the carrier wafer.

### Claim 19

A method comprising:
attaching a first wafer to a carrier wafer, wherein the first wafer comprises a semiconductor comprising a plurality of μLED arrays on a plurality of corresponding integrated circuits, wherein the carrier wafer has a diameter different than a diameter of the first wafer;
after attaching the first wafer to the carrier wafer, encapsulating the first wafer with a fill material;
forming at least one through substrate via in a substrate of at least one of the plurality of integrated circuits; and
thinning and planarizing the semiconductor and the fill material to a predetermined thickness.