# US 12,224,268 B2 · Fan-out packages providing enhanced mechanical strength and methods for forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,268 B2 - Document ID: US12224268B2 - Status: Granted - Kind: B2 - Application number: 18/360,734 - Filed: 2023-07-27 - Published: 2023-11-16 - Granted: 2025-02-11 - Earliest claimed: 2021-03-18 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Limited - Inventors: Jen-Yuan Chang; Chia-Ping Lai - Web page: https://patentgrep.com/patent/US12224268B2 ## CPC - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 90/00: Package configurations - H10P 72/74: {using temporarily an auxiliary support} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10W 72/0198: {batch processes} - H10W 72/072: {of bump connectors} - H10W 74/014: {using batch processing} - H10W 74/016: {using moulds} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10P 72/7416: {used during dicing or grinding} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/07254: {changes in dispositions} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/247: {Dispositions of multiple bumps} - H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 90/20: Configurations of stacked chips - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract An array of complementary die sets is attached to a carrier substrate. A continuous complementary-level molding compound layer is formed around the array of complementary die sets. An array of primary semiconductor dies is attached to the array of complementary die sets. A continuous primary-level molding compound layer is formed around the array of primary semiconductor dies. The bonded assembly is diced by cutting along directions that are parallel to edges of the primary semiconductor dies. The sidewalls of the complementary dies are azimuthally tilted relative to sidewalls of the primary semiconductor dies, or major crystallographic directions of a single crystalline material in the carrier substrate are azimuthally tilted relative to sidewalls of the primary semiconductor dies. ## Claims ### Claim 1 A fan-out package comprising: a primary semiconductor die that comprises a primary single crystalline semiconductor substrate having a <100> crystallographic direction along a first crystallographic lattice direction and is laterally surrounded by a primary-level molding compound layer, wherein the primary semiconductor die comprises a first pair of primary-die sidewalls that are parallel to a first horizontal direction and a second pair of primary-die sidewalls that are parallel to a second horizontal direction and perpendicular to the first horizontal direction; and a first complementary die that comprises a complementary single crystalline semiconductor substrate having a <100> crystallographic direction along a second crystallographic lattice direction and overlies or underlies, and is bonded to, the primary semiconductor die, is laterally surrounded by a complementary-level molding compound layer, and comprises a first pair of complementary-die sidewalls laterally extending along a third horizontal direction and comprises a second pair of complementary-die sidewalls laterally extending along a fourth horizontal direction that is perpendicular to the first pair of complementary-die sidewalls, wherein the fan-out package comprises at least one feature selected from: a first feature that the third horizontal direction is not parallel to the first horizontal direction or the second horizontal direction; a second feature that the first crystallographic lattice direction is azimuthally offset from the first horizontal direction and from the second horizontal direction by at least 0.5 degree; and a third feature that the second crystallographic lattice direction is azimuthally offset from the third horizontal direction and from the fourth horizontal direction by at least 0.5 degree. ### Claim 2 (depends on 1) The fan-out package of claim 1, wherein: the primary-level molding compound layer comprises a first pair of primary-mold sidewalls that are parallel to the first horizontal direction and a second pair of primary-mold sidewalls that are parallel to the second horizontal direction; the complementary-level molding compound layer comprises a first pair of complementary-mold sidewalls that are parallel to the first horizontal direction and a second pair of complementary-mold sidewalls that are parallel to the second horizontal direction; the first pair of primary-mold sidewalls and the first pair of complementary-mold sidewalls are located entirely within a pair of first vertical planes; and the second pair of primary-mold sidewalls and the second pair of complementary-mold sidewalls are located entirely within a pair of second vertical plane. ### Claim 3 (depends on 1) The fan-out package of claim 1, further comprising an inter-mold underfill layer located between the primary-level molding compound layer and the complementary-level molding compound layer and laterally surrounding an array of metal bonding structures providing electrical connection between the primary semiconductor die and the first complementary die. ### Claim 4 (depends on 3) The fan-out package of claim 3, wherein: the array of metal bonding structures comprises a rectangular array of solder balls bonded to a respective mating pair of metal pads or a rectangular array of solder material portions bonded to a respective pair of copper pillar bumps; and the rectangular array of solder balls has a first periodicity along the third horizontal direction and a second periodicity along the fourth horizontal direction. ### Claim 5 (depends on 1) The fan-out package of claim 1, wherein: the second crystallographic lattice direction is azimuthally offset from the first crystallographic lattice direction; and the fan-out package comprises at least one feature selected from: a first additional feature that the primary-level molding compound layer comprises a first pair of primary-mold sidewalls that are parallel to the first horizontal direction and a second pair of primary-mold sidewalls that are parallel to the second horizontal direction, and a second feature that the complementary-level molding compound layer comprises a first pair of complementary-mold sidewalls that are parallel to the first horizontal direction and a second pair of complementary-mold sidewalls that are parallel to the second horizontal direction. ### Claim 6 (depends on 1) The fan-out package of claim 1, further comprising a second complementary die that overlies or underlies, and is bonded to, the primary semiconductor die, laterally surrounded by the complementary-level molding compound layer, laterally spaced from the first complementary die, and comprising a third pair of complementary-die sidewalls laterally extending along a fifth horizontal direction that is not parallel to the first horizontal direction, the second horizontal direction, the third horizontal direction, or the fourth horizontal direction, and comprising a fourth pair of complementary-die sidewalls laterally extending along a sixth horizontal direction that is perpendicular to the fifth horizontal direction. ### Claim 7 (depends on 1) The fan-out package of claim 1, further comprising an additional complementary die that overlies or underlies, and is bonded to, the first complementary die, laterally surrounded by the complementary-level molding compound layer, and comprising a first additional pair of complementary-die sidewalls laterally extending along a first additional horizontal direction that is not parallel to the first horizontal direction, the second horizontal direction, the third horizontal direction, or the fourth horizontal direction, and comprising a second additional pair of complementary-die sidewalls laterally extending along a second additional horizontal direction that is perpendicular to the first additional horizontal direction. ### Claim 8 (depends on 1) The fan-out package of claim 1, wherein an angle between the first horizontal direction and the third horizontal direction is in a range from 0.5 degree to 89.5 degrees. ### Claim 9 (depends on 1) The fan-out package of claim 1, wherein an entire area of the first complementary die overlaps within an area of the primary semiconductor die in a plan view. ### Claim 10 (depends on 1) The fan-out package of claim 1, wherein: the primary semiconductor die comprises a system-on-chip (SoC) die; and the first complementary die comprises a high bandwidth memory (HBM) die including a vertical stack of static random access memory (SRAM) dies are interconnected to one another through microbumps. ### Claim 11 A fan-out package comprising: a primary semiconductor die that comprises a primary single crystalline semiconductor substrate having a first <100> crystallographic direction along a first crystallographic lattice direction and is laterally surrounded by a primary-level molding compound layer, wherein the primary semiconductor die comprises a first pair of primary-die sidewalls that are parallel to a first horizontal direction and a second pair of primary-die sidewalls that are parallel to a second horizontal direction and perpendicular to the first horizontal direction; and a first complementary die that comprises a complementary single crystalline semiconductor substrate having a second <100> crystallographic direction along a second crystallographic lattice direction and overlies or underlies, and is bonded to, the primary semiconductor die, is laterally surrounded by a complementary-level molding compound layer, and comprises a first pair of complementary-die sidewalls laterally extending along a third horizontal direction and comprises a second pair of complementary-die sidewalls laterally extending along a fourth horizontal direction that is perpendicular to the first pair of complementary-die sidewalls, wherein the fan-out package comprises at least one feature selected from: a first feature that the third horizontal direction is not parallel to the first horizontal direction or the second horizontal direction; a second feature that the first <100> crystallographic direction is aligned along a primary <100> crystallographic lattice direction that is azimuthally offset from the first horizontal direction and from the second horizontal direction by at least 0.5 degree; and a third feature that the second <100> crystallographic direction is aligned along a complementary <100> crystallographic lattice direction that is azimuthally offset from the first horizontal direction and from the second horizontal direction by at least 0.5 degree. ### Claim 12 (depends on 11) The fan-out package of claim 11, wherein the third horizontal direction is parallel to the first horizontal direction; and the fourth horizontal direction is parallel to the second horizontal direction. ### Claim 13 (depends on 11) The fan-out package of claim 11, wherein: the third horizontal direction is azimuthally offset from the first horizontal direction by an azimuthal offset angle; the fourth horizontal direction is azimuthally offset from the second horizontal direction by the azimuthal offset angle; and the azimuthal offset angle is in a range from 0.5 degree to 89.5 degrees. ### Claim 14 (depends on 11) The fan-out package of claim 11, wherein: the primary die comprises an array of first primary metal bump structures; the first complementary die comprises an array of first complementary metal bump structures that are bonded to the array of first primary metal bump structures through an array of first solder material portions; and an inter-mold underfill layer laterally surrounds the array of first solder material portions. ### Claim 15 (depends on 11) The fan-out package of claim 11, wherein: the primary-level molding compound layer comprises primary-mold sidewalls that are parallel to the first horizontal direction or the second horizontal direction; and the complementary-level molding compound layer comprises complementary-mold sidewalls that are vertically coincident with the primary-mold sidewalls. ### Claim 16 A fan-out package comprising: a primary semiconductor die that comprises a primary single crystalline semiconductor substrate having a first <100> crystallographic direction along a first crystallographic lattice direction, and comprising a first pair of primary-die sidewalls that are parallel to a first horizontal direction and a second pair of primary-die sidewalls that are parallel to a second horizontal direction and perpendicular to the first horizontal direction; and a first complementary die that comprises a complementary single crystalline semiconductor substrate having a second <100> crystallographic direction along a second crystallographic lattice direction and overlies or underlies, and is bonded to, the primary semiconductor die, and comprising a first pair of complementary-die sidewalls laterally extending along a third horizontal direction and comprises a second pair of complementary-die sidewalls laterally extending along a fourth horizontal direction that is perpendicular to the first pair of complementary-die sidewalls, wherein the fan-out package comprises at least one feature selected from: a first feature that the third horizontal direction is not parallel to the first horizontal direction or the second horizontal direction; a second feature that the first <100> crystallographic direction is aligned along a primary <100> crystallographic lattice direction that is azimuthally offset from the first horizontal direction and from the second horizontal direction by at least 0.5 degree; and a third feature that the second <100> crystallographic direction is aligned along a complementary <100> crystallographic lattice direction that is azimuthally offset from the first horizontal direction and from the second horizontal direction by at least 0.5 degree. ### Claim 17 (depends on 16) The fan-out package of claim 16, wherein the third horizontal direction is not parallel to the first horizontal direction or the second horizontal direction. ### Claim 18 (depends on 16) The fan-out package of claim 16, further comprising a second complementary die comprising a third pair of complementary-die sidewalls laterally extending along a fifth horizontal direction that is not parallel to the first horizontal direction, the second horizontal direction, the third horizontal direction, or the fourth horizontal direction, and comprising a fourth pair of complementary-die sidewalls laterally extending along a sixth horizontal direction that is perpendicular to the fifth horizontal direction. ### Claim 19 (depends on 18) The fan-out package of claim 18, wherein: the second complementary die is bonded to the primary semiconductor dies through an array of metal bonding structures that comprises a rectangular array of solder balls bonded to a respective mating pair of metal pads or a rectangular array of solder material portions bonded to a respective pair of copper pillar bumps; and the rectangular array of solder balls has a bump periodicity along the fifth horizontal direction and an additional bump periodicity along the sixth horizontal direction. ### Claim 20 (depends on 16) The fan-out package of claim 16, further comprising a second complementary die comprising a third pair of complementary-die sidewalls laterally extending along a first additional horizontal direction that is not parallel to the first horizontal direction, the second horizontal direction, the third horizontal direction, or the fourth horizontal direction, and comprising a fourth pair of complementary-die sidewalls laterally extending along a second additional horizontal direction that is perpendicular to the first additional horizontal direction, wherein: the second complementary die is bonded to the first complementary die through an array of metal bonding structures that comprises a rectangular array of solder balls bonded to a respective mating pair of metal pads or a rectangular array of solder material portions bonded to a respective pair of copper pillar bumps; and the rectangular array of solder balls has a bump periodicity along the first additional horizontal direction and an additional bump periodicity along the second additional horizontal direction.