# US 12,224,267 B2 · Chip interconnecting method, interconnect device and method for forming chip packages

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- Number: US 12,224,267 B2
- Document ID: US12224267B2
- Status: Granted
- Kind: B2
- Application number: 17/542,417
- Filed: 2021-12-04
- Published: 2022-06-09
- Granted: 2025-02-11
- Earliest claimed: 2020-12-04
- Assignees: Yibu Semiconductor Co., Ltd.
- Applicants: Yibu Semiconductor Co., Ltd.
- Inventors: Weiping Li
- Web page: https://patentgrep.com/patent/US12224267B2

## CPC

- H10W 70/611: {for connecting multiple chips together}
- H10W 90/00: Package configurations
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/095: {of vias therein}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 70/688: {Flexible insulating substrates}
- H10W 72/0198: {batch processes}
- H10W 72/50: Bond wires
- H10W 72/851: {Dispositions of multiple connectors or interconnections}
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/07221: {Aligning}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/725: {between a chip and a laterally-adjacent insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a chip interconnecting method, an interconnect device and a method for forming a chip interconnection package. The method comprises arranging at least one chipset on a carrier, each chipset including at least a first chip and a second chip. A contact surface (or diameter) of each of the first bumps is smaller than that of any of the second bumps. The method further comprises attaching an interconnect device to the first chip and the second chip, the interconnect device including first pads for bonding to corresponding bumps on the first chip and second pads for bonding to corresponding bumps on the second chip. Attaching the interconnect device includes aligning the plurality of first pads with the corresponding bumps on the first chip whereby the plurality of second pads are self-aligned for bonding to the plurality of second bumps.

## Claims

### Claim 1

A method of chip interconnection, comprising:
arranging at least one chipset on a surface of a carrier, each chipset including at least a first chip and a second chip, the first chip including first bumps formed on a first portion of a front surface of the first chip, the second chip including second bumps formed on a first portion of a front surface of the second chip, wherein the first bumps include a plurality of first bumps having a first density and the second bumps include a plurality of second bumps having a second density, the first density being higher than the second density; and
attaching an interconnect device to the first portion of the front surface of the first chip and to the first portion of the front surface of the second chip, the interconnect device having a first side and a plurality pads formed on the first side, the plurality of pads including a plurality of first pads for respectively bonding to the plurality of first bumps having the first density on the first chip and a plurality of second pads for respectively bonding to the plurality of second bumps having the second density on the second chip, wherein attaching the interconnect device includes:
aligning and bonding the plurality of first pads with respective ones of the plurality of first bumps having the first density on the first chip; and
after a placement position of the interconnect device is fixed due to the plurality of first pads being respectively bonded with respective ones of the plurality of first bumps, bonding the plurality of second pads to respective ones of the plurality of second bumps having the second density on the second chip by self-alignment bonding.

### Claim 2 (depends on 1)

The method of claim 1, wherein an area or diameter of a contact surface of each of the first bumps is smaller than that of any of the second bumps.

### Claim 3 (depends on 1)

The method of claim 1, wherein the plurality of second pads correspond, respectively, to the plurality of first pads, and wherein the interconnect device includes a fan-out circuit interconnecting, respectively, the plurality of first pads with corresponding ones of the plurality of second pads to enable the first chip to be electrically connected to the second chip through the interconnect device.

### Claim 4 (depends on 1)

The method of claim 1, wherein each interconnect device includes vertical interconnect vias.

### Claim 5 (depends on 1)

The method of claim 1, wherein each interconnect device includes an active device.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first chip further includes third bumps formed on a second portion of the front surface of the first chip, and the second chip further includes fourth bumps formed on a second portion of the front surface of the second chip, the interconnect device includes a fan-out circuit interconnecting the plurality of first pads with corresponding ones of the plurality of second pads;
the method further comprising:
forming a molded encapsulation layer over the carrier whereby the first chip, the second chip and the interconnect device are embedded in the molded encapsulation layer;
thinning one side of the molded encapsulation layer that is facing away from the carrier to expose the third bumps and the fourth bumps;
forming fifth bumps on the one side of the molded encapsulation layer facing away from the carrier, wherein each of the fifth bumps is electrically coupled to at least one of the first third bumps and the fourth bumps; and
removing the carrier.

### Claim 7 (depends on 6)

The method of claim 6, wherein the at least one chipset includes multiple chipsets, the method further comprising: after removing the carrier, dicing the molded encapsulation layer with the multiple chipsets embedded therein to obtain a plurality of unit packages, wherein each unit package includes a chipset.

### Claim 8 (depends on 1)

The method of claim 1, further comprising forming a molded encapsulation layer over the carrier, wherein the interconnect device is attached to the first portion of the front surface of the first chip and the first portion of the front surface of the second chip before the first chip and the second chip are embedded or partially embedded in the molded encapsulation layer.

### Claim 9 (depends on 6)

The method of claim 6, wherein the first chip is electrically connected to the second chip through the interconnect device before the first chip and the second chip are embedded or partially embedded.

### Claim 10 (depends on 1)

The method of claim 1, further comprising forming a molded encapsulation layer over the carrier, wherein the interconnect device is attached to the first portion of the front surface of the first chip and the first portion of the front surface of the second chip before the first chip and the second chip are embedded or partially embedded in any portion of the molded encapsulation layer.

### Claim 11 (depends on 6)

The method of claim 6, wherein the first chip is electrically connected to the second chip through the interconnect device before the first chip and the second chip are embedded or partially embedded in any portion of the molded encapsulation layer.

### Claim 12 (depends on 1)

The method of claim 1, wherein the first bumps are solder bumps, and the second bumps are solder bumps.

### Claim 13 (depends on 12)

The method of claim 12, wherein an area or diameter of a contact surface of each of the first bumps is smaller than that of any of the second bumps.

### Claim 14 (depends on 1)

The method of claim 1, wherein the interconnect device includes through silicon vias extending through the interconnect device between the first side and an opposing second side, the method further comprising forming I/O pins on a surface on the second side of the interconnect device.

### Claim 15 (depends on 6)

The method of claim 6, further comprising:
forming a redistribution layer on the one side of the molded encapsulation layer facing away from the carrier, wherein the fifth bumps are formed on the redistribution layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the fifth bumps on the one side of the molded encapsulation layer facing away from the carrier comprises:
forming a solder covering layer on the one side of the molded encapsulation layer facing away from the carrier.

### Claim 17 (depends on 1)

The method of claim 1, wherein each of the plurality of second bumps has a contact area that is greater than a contact area of any of the plurality of first bumps and provides sufficient tolerance to allow the plurality of second pads to be respectively bonded by self-alignment bonding to the plurality of second bumps based on self-tension of the interconnect device.

### Claim 18 (depends on 6)

The method of claim 6, wherein each of the plurality of second bumps has a contact area that is greater than a contact area of any of the plurality of first bumps to provide sufficient tolerance to allow the plurality of second pads be respectively bonded by self-alignment bonding to the plurality of second bumps based on self-tension of the interconnect device.

### Claim 19 (depends on 1)

The method of claim 1, wherein the each chip set further includes a third chip and a fourth chip, the third chip including third bumps formed on a first portion of a front surface of the third chip, the fourth chip including fourth bumps formed on a first portion of a front surface of the second chip, wherein the third bumps include a plurality of third bumps having a third density and the fourth bumps include a plurality of fourth bumps having a fourth density, the third density being higher than the fourth density, the method further comprising:
mounting the third chip over a second portion of the front surface of one of the third chip and the fourth chip, and mounting the fourth chip over a second portion of the front surface of the other one of the third chip and the fourth chip;
attaching an additional interconnect device to the first portion of the front surface of the third chip and to the first portion of the front surface of the fourth chip, the additional interconnect device having a first side and a plurality pads formed on the first side, the plurality of pads including a plurality of third pads for respectively bonding to the plurality of third bumps having the third density on the third chip and a plurality of fourth pads for respectively bonding to the plurality of fourth bumps having the fourth density on the fourth chip, wherein attaching the additional interconnect device includes:
aligning and bonding the plurality of third pads to respective ones of the plurality of third bumps having the third density on the third chip; and
after a placement position of the additional interconnect device is fixed due to the plurality of third pads being respectively bonded with respective ones of the plurality of third bumps, bonding the plurality of fourth pads to respective ones of the plurality of fourth bumps having the fourth density on the fourth chip by self-alignment bonding.