# US 12,224,266 B2 · Semiconductor packages including passive devices and methods of forming same

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- Number: US 12,224,266 B2
- Document ID: US12224266B2
- Status: Granted
- Kind: B2
- Application number: 18/501,314
- Filed: 2023-11-03
- Published: 2024-02-22
- Granted: 2025-02-11
- Earliest claimed: 2020-07-21
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Shin-Puu Jeng; Po-Yao Chuang; Shuo-Mao Chen
- Web page: https://patentgrep.com/patent/US12224266B2

## CPC

- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 90/00: Package configurations
- H01G 2/06: specially adapted for mounting on a printed-circuit support
- H01G 4/232: electrically connecting two or more layers of a stacked or rolled capacitor
- H01G 4/33: Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)}
- H01G 4/38: Multiple capacitors, i.e. structural combinations of fixed capacitors
- H10W 20/496: {Capacitor integral with wiring layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/685: comprising multiple insulating layers
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H01G 4/012: Form of non-self-supporting electrodes
- H01G 4/40: Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
- H10D 1/665: {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors}
- H10D 1/716: {having vertical extensions}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9413: {on encapsulations}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An embodiment is a structure including a first semiconductor device and a second semiconductor device, a first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors.

## Claims

### Claim 1

A structure comprising:
a stack of semiconductor devices, each of the semiconductor devices comprising:
trench capacitors on a substrate; and
through vias extending through the substrate, the through vias being electrically coupled to the trench capacitors;
first conductive connectors between each of the semiconductor devices of the stack of semiconductor devices, the first conductive connectors mechanically and electrically bonding the adjacent semiconductor devices together;
underfill between the adjacent semiconductor devices and surrounding the first conductive connectors;
a first encapsulant on sidewalls of the stack of semiconductor devices and the underfill; and
second conductive connectors electrically coupled to a lowermost semiconductor device of the stack of semiconductor devices, the second conductive connectors being on an opposite side of the lowermost semiconductor device as the first conductive connectors.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the trench capacitors in each of the semiconductor devices are electrically coupled together in parallel.

### Claim 3 (depends on 1)

The structure of claim 1, further comprising:
a first redistribution structure on the first encapsulant and the stack of semiconductor devices, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the second conductive connectors and the stack of semiconductor devices.

### Claim 4 (depends on 3)

The structure of claim 3, wherein the first redistribution structure is between the second conductive connectors and the stack of semiconductor devices.

### Claim 5 (depends on 4)

The structure of claim 4, further comprising:
a first integrated circuit package comprising at least one integrated circuit die, the at least one integrated circuit die comprising a plurality of active devices; and
a second encapsulant on sidewalls of the first encapsulant and the first integrated circuit package.

### Claim 6 (depends on 5)

The structure of claim 5, further comprising:
a second redistribution structure on the second encapsulant, the first integrated circuit package, and the stack of semiconductor devices, the second redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first integrated circuit package and the stack of semiconductor devices.

### Claim 7 (depends on 6)

The structure of claim 6, further comprising:
a package substrate bonded to the second redistribution structure.

### Claim 8 (depends on 1)

The structure of claim 1, wherein the second conductive connectors are larger than the first conductive connectors.

### Claim 9

A method comprising:
forming a first stack of semiconductor devices, wherein forming the first stack comprises:
bonding a first semiconductor device to a second semiconductor device using first conductive connectors, each of the first and second semiconductor devices comprising:
capacitors on a substrate; and
through vias extending through the substrate, the through vias being electrically coupled to the capacitors;
forming a second stack of semiconductor devices, wherein forming the second stack comprises:
bonding a third semiconductor device to a fourth semiconductor device using second conductive connectors, each of the third and fourth semiconductor devices comprising:
capacitors on a substrate; and
through vias extending through the substrate, the through vias being electrically coupled to the capacitors;
attaching the first and second stacks to a first carrier substrate;
encapsulating the first and second stacks with an encapsulant;
removing the first carrier substrate; and
singulating the first and second stacks forming first and second encapsulated stacks of semiconductor devices.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
forming a third set of conductive connectors on the first and second stacks of semiconductor devices.

### Claim 11 (depends on 10)

The method of claim 10, wherein the third set of conductive connectors are formed before singulating the first and second stacks.

### Claim 12 (depends on 10)

The method of claim 10, wherein the third set of conductive connectors are formed after encapsulating the first and second stacks with the encapsulant.

### Claim 13 (depends on 9)

The method of claim 9, further comprising:
before singulating the first and second stacks of semiconductor devices, forming a first redistribution structure on the encapsulant and the first and second stacks of semiconductor devices, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the through vias of the first and second stacks of semiconductor devices.

### Claim 14 (depends on 9)

The method of claim 9 further comprising:
forming a first package comprising:
forming a first integrated circuit package comprising at least one integrated circuit die, the at least one integrated circuit die comprising a plurality of active devices;
encapsulating the first encapsulated stack of semiconductor devices and the first integrated circuit package with a second encapsulant; and
forming a second redistribution structure on the second encapsulant, the first integrated circuit package, and the first encapsulated stack of semiconductor devices, the second redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the second redistribution structure being electrically coupled to the first integrated circuit package and the first encapsulated stack of semiconductor devices.

### Claim 15

A package structure comprising:
a first package comprising:
a stack of dies, each of the dies comprising a plurality of capacitors on a substrate and a through via extending through the substrate;
a first integrated circuit package comprising an integrated circuit die, the integrated circuit die comprising active devices;
a first encapsulant on sidewalls of the first package and the first integrated circuit package;
a first redistribution structure on the first encapsulant, the first integrated circuit package, and the first package, the first redistribution structure being electrically coupled to the first integrated circuit package and the first package; and
a first package substrate bonded to the first redistribution structure.

### Claim 16 (depends on 15)

The package structure of claim 15, wherein the plurality of capacitors of one of the stack of dies is electrically coupled together in parallel.

### Claim 17 (depends on 15)

The package structure of claim 15, wherein a first die of the stack of dies comprises a first plurality of capacitors and a second die of the stack of dies comprises a second plurality of capacitors, the first plurality of capacitors and the second plurality of capacitors being electrically coupled together in parallel.

### Claim 18 (depends on 15)

The package structure of claim 15, wherein the plurality of capacitors of each of the stack of dies is a plurality of trench capacitors.

### Claim 19 (depends on 15)

The package structure of claim 15, wherein the first package further comprises:
a second redistribution structure on a bottommost die of the stack of dies, the second redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the second redistribution structure being electrically coupled to the through via of bottommost die of the stack of dies and to the metallization patterns of the first redistribution structure.

### Claim 20 (depends on 19)

The package structure of claim 19 further comprising:
a first set of conductive connectors on the first redistribution structure; and
a package substrate mechanically and electrically coupled to the first redistribution structure by the first set of conductive connectors.