# US 12,224,264 B2 · Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate

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- Number: US 12,224,264 B2
- Document ID: US12224264B2
- Status: Granted
- Kind: B2
- Application number: 18/385,167
- Filed: 2023-10-30
- Published: 2024-02-22
- Granted: 2025-02-11
- Earliest claimed: 2017-03-31
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Rahul Jain; Ji Yong Park; Kyu Oh Lee
- Web page: https://patentgrep.com/patent/US12224264B2

## CPC

- H10W 72/072: {of bump connectors}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07254: {changes in dispositions}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

## Claims

### Claim 1

A semiconductor device, comprising:
a die interconnect substrate, comprising:
a substrate structure comprising an electrically insulating substrate; and
a bridge die embedded in the electrically insulating substrate of the substrate structure, the bridge die comprising a silicon substrate, wherein a first portion of the electrically insulating substrate is on sidewalls of the bridge die and on a front side of the bridge die;
a core embedded in the electrically insulating substrate of the substrate structure, the core below the bridge die;
a lateral wire beneath the bridge die, the lateral wire extending an entirety of the bridge die, wherein a second portion of the electrically insulating substrate is beneath the lateral wire;
a first interface structure coupled to a first bridge die pad of the front side of the bridge die, the first interface structure through the first portion of the electrically insulating substrate;
a second interface structure coupled to a second bridge die pad of the front side of the bridge die, the second interface structure through the first portion of the electrically insulating substrate;
a first substrate interconnect through the first portion of the electrically insulating substrate; and
a second substrate interconnect through the first portion of the electrically insulating substrate; and
a first die coupled to the bridge die by the first interface structure, the first die also coupled to the first substrate interconnect, wherein the first die is coupled to the lateral wire; and
a second die coupled to the bridge die by the second interface structure, the second die also coupled to the second substrate interconnect.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first die is a memory die.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first die is a processor die.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first die is a memory die, and the second die is a processor die.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first bridge die pad of the front side of the bridge die is electrically coupled to the second bridge die pad of the front side of the bridge die.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the first and second substrate interconnects each have a bottom surface below a bottom surface of the bridge die.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the electrically insulating substrate comprises an electrically insulating core.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the electrically insulating substrate is a polymer-based substrate.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the electrically insulating substrate is an epoxy-based substrate.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the electrically insulating substrate is a laminate-based substrate.

### Claim 11

A semiconductor device, comprising:
a die interconnect substrate, comprising:
a substrate structure; and
a bridge die embedded in the substrate structure, the bridge die comprising a silicon substrate;
a core embedded in the electrically insulating substrate of the substrate structure, the core below the bridge die;
a lateral wire beneath the bridge die, the lateral wire extending an entirety of the bridge die, wherein a portion of the substrate structure is beneath the lateral wire;
a first interface structure coupled to a first bridge die pad of the bridge die;
a second interface structure coupled to a second bridge die pad of the bridge die;
a first substrate interconnect at a first side of the bridge die, the first substrate interconnect electrically insulated from the bridge die; and
a second substrate interconnect at a second side of the bridge die, the second substrate interconnect electrically insulated from the bridge die; and
a first die coupled to the bridge die by the first interface structure, the first die also coupled to the first substrate interconnect, wherein the first die is coupled to the lateral wire; and
a second die coupled to the bridge die by the second interface structure, the second die also coupled to the second substrate interconnect.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the first die is a memory die.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the first die is a processor die.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein the first die is a memory die, and the second die is a processor die.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein the first bridge die pad of the bridge die is electrically coupled to the second bridge die pad of the bridge die.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, wherein the first and second substrate interconnects each have a bottom surface below a bottom surface of the bridge die.

### Claim 17 (depends on 11)

The semiconductor device of claim 11, wherein the substrate structure comprises an electrically insulating core.

### Claim 18 (depends on 11)

The semiconductor device of claim 11, wherein the substrate structure is a polymer-based substrate structure.

### Claim 19 (depends on 11)

The semiconductor device of claim 11, wherein the substrate structure is an epoxy-based substrate structure.

### Claim 20 (depends on 11)

The semiconductor device of claim 11, wherein the substrate structure is a laminate-based substrate structure.