# US 12,224,262 B2 · Substrate bonding apparatus and method of manufacturing semiconductor device by using the same

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- Number: US 12,224,262 B2
- Document ID: US12224262B2
- Status: Granted
- Kind: B2
- Application number: 18/638,947
- Filed: 2024-04-18
- Published: 2024-08-08
- Granted: 2025-02-11
- Earliest claimed: 2019-08-20
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Taeyeong Kim; Ilyoung Han; Hoechul Kim
- Web page: https://patentgrep.com/patent/US12224262B2

## CPC

- H10W 72/011: {Apparatus therefor}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/019: {of bond pads}
- H10W 72/07125: {Means for controlling the bonding environment, e.g. valves or vacuum pumps}
- H10W 72/07141: {Means for applying energy, e.g. ovens or lasers}
- H10W 72/07178: {Means for aligning}
- H10W 72/07183: {Means for monitoring}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure}
- H10W 80/161: {Aligning}
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/701: {characterised by the pads after the direct bonding}
- H10W 80/732: {having shape changed during the connecting}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A substrate bonding method and apparatus are described. The substrate bonding apparatus is used to bond a first substrate to a second substrate. The bonding apparatus includes a first bonding chuck configured to hold the first substrate on a first surface of the first bonding chuck; a second bonding chuck configured to hold the second substrate on a second surface of the second bonding chuck, the second surface facing the first surface of the first bonding chuck; a seal arranged between the first bonding chuck and the second bonding chuck and adjacent to at least one edge of the first substrate and at least one edge of the second substrate; and a process gas supply device configured to supply a process gas to a bonding space surrounded by the seal.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
aligning a second bonding chuck, on which a second substrate is arranged, with a first bonding chuck, on which a first substrate is arranged, such that the second bonding chuck is arranged over the first bonding chuck;
forming a bonding space between the first bonding chuck and the second bonding chuck by securing a seal between the first bonding chuck and the second bonding chuck, the bonding space being surrounded by the seal, and the seal surrounding an edge of the first substrate and an edge of the second substrate;
supplying a process gas to the bonding space; and
bonding the first substrate to the second substrate.

### Claim 2 (depends on 1)

The method of claim 1, wherein
an upper portion of the seal is coupled to the second bonding chuck,
a lower portion of the seal is detachably coupled to the first bonding chuck, and
the lower portion of the seal is coupled to the first bonding chuck by a vacuum pressure applied to a vacuum groove arranged in the first bonding chuck.

### Claim 3 (depends on 1)

The method of claim 1, wherein
the supplying of the process gas to the bonding space comprises:
sensing a temperature of the bonding space; and,
when the sensed temperature of the bonding space is outside a pre-set target temperature range, adjusting a temperature of the process gas supplied to the bonding space.

### Claim 4 (depends on 3)

The method of claim 3, wherein the target temperature range is from about 15° C. to about 25° C.

### Claim 5 (depends on 1)

The method of claim 1, wherein
the supplying of the process gas to the bonding space comprises:
sensing a pressure of the bonding space; and,
when the sensed pressure of the bonding space is outside a pre-set target pressure range, adjusting a pressure of the process gas supplied to the bonding space.

### Claim 6 (depends on 5)

The method of claim 5, wherein the target pressure range is from about 1 atm to about 1.5 atm.

### Claim 7 (depends on 1)

The method of claim 1, further comprising
after the bonding of the first substrate to the second substrate, discharging gas from the bonding space surrounded by the seal and supplying a purge gas to the bonding space.

### Claim 8 (depends on 1)

The method of claim 1, wherein the process gas is helium (He) gas.

### Claim 9

A method of manufacturing a semiconductor device, the method comprising:
providing a first substrate disposed on a first bonding chuck and a second substrate disposed on a second bonding chuck, wherein the first substrate and the second substrate are located between the first bonding chuck and the second bonding chuck;
providing a seal in direct contact with the first bonding chuck and the second bonding chuck to enclose a bonding space between the first bonding chuck and the second bonding chuck;
supplying a process gas to the bonding space, the process gas having less reactivity with the first substrate and the second substrate compared with ambient gas outside the bonding space; and
bonding the first substrate to the second substrate.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
supplying a purge gas to the bonding space after bonding the first substrate to the second substrate to discharge the process gas from the bonding space.