# US 12,224,261 B2 · Mixed hybrid bonding structures and methods of forming the same

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- Number: US 12,224,261 B2
- Document ID: US12224261B2
- Status: Granted
- Kind: B2
- Application number: 17/488,174
- Filed: 2021-09-28
- Published: 2022-01-20
- Granted: 2025-02-11
- Earliest claimed: 2019-09-26
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Shawna Liff; Adel Elsherbini; Johanna Swan; Nagatoshi Tsunoda; Jimin Yao
- Web page: https://patentgrep.com/patent/US12224261B2

## CPC

- H10W 70/69: Insulating materials thereof
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/68: Shapes or dispositions thereof
- H10W 70/695: Organic materials
- H10W 72/013: {of die-attach connectors}
- H10W 74/473: {containing a filler}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7428: {used to support diced chips prior to mounting}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 72/07331: {Connecting techniques}
- H10W 72/322: {Multilayered die-attach connectors, e.g. a coating on a top surface of a core}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/951: {Materials of bond pads}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/314: {characterized by direct bonding of pads or other interconnections}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.

## Claims

### Claim 1

A microelectronic structure comprising:
a substrate layer comprising:
a composite dielectric layer comprising an organic dielectric material and an inorganic filler material; and
one or more conductive substrate interconnect structures within the composite organic dielectric layer; and
a die comprising a die layer, the die layer comprising:
a die dielectric layer; and
one or more conductive die interconnect structures within the die dielectric layer, wherein the die layer is in direct contact with the substrate layer, and wherein at least one of the one or more conductive substrate interconnect structures is in direct contact with at least one of the one or more conductive die interconnect structures.

### Claim 2 (depends on 1)

The microelectronic structure of claim 1 wherein at least one of the conductive die or the conductive substrate interconnect structures has a coefficient of thermal expansion (CTE), in a direction normal to a bond interface between the substrate layer and the die layer that is at least 30 percent greater than a CTE of the composite organic dielectric layer.

### Claim 3 (depends on 1)

The microelectronic structure of claim 1 further comprising a coat layer in direct contact with the composite dielectric layer and in direct contact with the die dielectric layer.

### Claim 4 (depends on 3)

The microelectronic structure of claim 3 wherein the coat layer has a thickness between 10 nm and 1600 nm.

### Claim 5 (depends on 1)

The microelectronic structure of claim 1 wherein the organic dielectric material comprises one or more of an epoxy material or a spin on glass material, and wherein the inorganic filler material comprises one or more of silica, a silsesquioxane material, silicon nitride, silicon carbide, aluminum oxide, or diamond, and wherein the organic dielectric material comprises between about 70% by weight to about 95% by weight of the inorganic filler material.

### Claim 6 (depends on 5)

The microelectronic structure of claim 5, wherein the die dielectric layer comprises an inorganic dielectric material.

### Claim 7 (depends on 1)

The microelectronic structure of claim 1 wherein at least a portion of the inorganic filler material is covalently bonded with the inorganic dielectric layer of the die layer.

### Claim 8 (depends on 1)

The microelectronic structure of claim 1 wherein the one or more conductive die interconnect structures include a first conductive die interconnect structure adjacent to a second conductive die interconnect structure, wherein a pitch between the first conductive die interconnect structure and the second conductive die interconnect structure is less than 50 microns.

### Claim 9 (depends on 1)

The microelectronic structure of claim 1 wherein a top surface of the substrate layer, a top surface of the die layer, and top surfaces of the one or more conductive die interconnect structures and the one or more conductive die interconnect structures are free of solder, and are free of underfill material.

### Claim 10

A microelectronic structure comprising:
a package substrate;
a dielectric layer on the package substrate, wherein at least a portion of the dielectric layer comprises an inorganic filler material within an organic dielectric material;
one or more conductive substrate interconnect structures within the organic dielectric layer;
a die comprising a die layer, the die layer comprising:
a die dielectric layer; and
one or more conductive die interconnect structures within the die dielectric layer, wherein the die layer is directly on the dielectric layer, wherein the one or more conductive substrate interconnect structures are directly on the one or more conductive die interconnect structures.

### Claim 11 (depends on 10)

The microelectronic structure of claim 10 wherein the die dielectric layer comprises a die organic dielectric material, wherein a first inorganic filler material is within the die organic dielectric material, and wherein the dielectric layer comprises an organic dielectric material, and a second inorganic filler material is within the organic dielectric material.

### Claim 12 (depends on 10)

The microelectronic structure of claim 10 wherein the dielectric layer comprises a first portion comprising an organic dielectric material, wherein an inorganic filler material is within the first portion of the organic dielectric material, and a second portion comprises an inorganic dielectric material that is free of an inorganic filler material, wherein the second portion is covalently bonded to the die dielectric layer, and wherein the inorganic filler material of the first portion is covalently bonded to the die dielectric layer.

### Claim 13 (depends on 12)

The microelectronic structure of claim 12 wherein the first portion comprises between 70 percent by weight and 95 percent by weight of the inorganic filler material.

### Claim 14 (depends on 10)

The microelectronic structure of claim 10 wherein the one or more conductive substrate interconnect structures and the one or more conductive die interconnect structures are free of a seed layer at an interface plane.

### Claim 15 (depends on 10)

The microelectronic structure of claim 10 wherein the microelectronic structure is communicatively coupled to one or more of a central processing unit, a field-programmable gate array, a system on a chip, or a graphics processing unit, or a combination thereof.