# US 12,224,259 B2 · Clamped semiconductor wafers and semiconductor devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,259 B2 - Document ID: US12224259B2 - Status: Granted - Kind: B2 - Application number: 17/718,021 - Filed: 2022-04-11 - Published: 2023-10-12 - Granted: 2025-02-11 - Earliest claimed: 2022-04-11 - Assignees: SanDisk Technologies LLC - Applicants: Western Digital Technologies, Inc. - Inventors: Kirubakaran Periyannan; Daniel Linnen; Jayavel Pachamuthu - Web page: https://patentgrep.com/patent/US12224259B2 ## CPC - H10W 90/00: Package configurations - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W 80/00: Direct bonding of chips, wafers or substrates - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 72/931: {Shapes of bond pads} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads} - H10W 72/967: {Multiple bond pads having different functions} - H10W 80/732: {having shape changed during the connecting} - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/752: {between stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Clamped semiconductor wafers and clamped semiconductor devices include reservoirs filled with a flowable metal which hardens to allow the wafers/devices to be shipped or stored. The hardened metal may also be reflowed to a liquid to allow clamping of the semiconductor wafers together and to allow clamping of the semiconductor packages together. The flowable metal may be filled into the reservoirs as a liquid or paste. Thereafter, the flowable metal may be cooled to harden the flowable metal into a clamping member. ## Claims ### Claim 1 A semiconductor wafer, comprising: first and second opposed major surfaces, the first surface defining a first direction parallel to the first surface, and a second direction between the first and second opposed major surfaces; a dielectric layer adjacent the first major surface; integrated circuits formed in the dielectric layer; bond pads in the first major surface, the bond pads electrically coupled to the integrated circuits; and a set of one or more reservoirs formed in the dielectric layer and open at the first major surface, the set of one or more reservoirs configured to receive a flowable metal to clamp the semiconductor wafer to a second semiconductor wafer upon hardening of the flowable metal in the set of one or more reservoirs, a reservoir of the set of one or more reservoirs comprising: a first section having a first sub-section extending in the first direction, and a second sub-section extending in the second direction, and a second section having a third sub-section extending in the first direction and a fourth sub-section extending in the second direction, wherein the first and second sections are connected to each other through one or more additional sections formed in the second semiconductor wafer. ### Claim 2 (depends on 1) The semiconductor wafer of claim 1, wherein a reservoir from the set of one or more reservoirs comprises a base section distal from the first major surface and a neck section more proximal to the first major surface than the base section, and wherein the base section is wider than the neck section. ### Claim 3 (depends on 1) The semiconductor wafer of claim 1, wherein the set of one or more reservoirs extend to a depth partially through a depth of the dielectric layer. ### Claim 4 (depends on 1) The semiconductor wafer of claim 1, wherein the set of one or more reservoirs are positioned so as not to interfere with positions of the integrated circuits and bond pads. ### Claim 5 (depends on 1) The semiconductor wafer of claim 1, further comprising a semiconductor die comprising the integrated circuits, wherein the set of one or more reservoirs comprise a plurality of reservoirs surrounding a footprint of the semiconductor die. ### Claim 6 (depends on 1) The semiconductor wafer of claim 1, further comprising a semiconductor die comprising the integrated circuits, wherein the set of one or more reservoirs comprise one or more reservoirs within a footprint of the semiconductor die. ### Claim 7 (depends on 1) The semiconductor wafer of claim 1, further comprising a metal within the set of one or more reservoirs, wherein the metal is configured to be a liquid or paste at a first temperature and a solid at a second temperature lower than the first temperature. ### Claim 8 (depends on 7) The semiconductor wafer of claim 7, wherein the metal is configured to fill at least a portion of a first reservoir of the set of one or more reservoirs in the wafer, and to at least partially fill a second reservoir of the second wafer, the first and second reservoirs aligned with each other, to clamp the wafer to the second wafer when the metal is at the second temperature. ### Claim 9 (depends on 7) The semiconductor wafer of claim 7, wherein the metal is configured to contract when moving from the first temperature to the second temperature to pull the wafer and the second wafer tightly together. ### Claim 10 (depends on 1) The semiconductor wafer of claim 1, wherein the integrated circuits comprise one of memory arrays and CMOS logic circuits, and wherein the second wafer comprises the other of the memory arrays and CMOS logic circuits. ### Claim 11 A semiconductor die, comprising: first and second opposed major surfaces; a dielectric layer adjacent the first major surface; integrated circuits formed in the dielectric layer; bond pads in the first major surface, the bond pads electrically coupled to the integrated circuits; and a set of one or more reservoirs formed in the dielectric layer and open at the first major surface, the set of one or more reservoirs configured to receive a flowable metal to clamp the semiconductor die to a second semiconductor die upon hardening of the flowable metal in the set of one or more reservoirs, a reservoir of the set of one or more reservoirs comprising: a first “T”-shaped section having a first sub-section extending in a first direction, and a second sub-section extending in a second direction orthogonal to the first direction, and a second section having a third sub-section extending in the first direction and a fourth sub-section extending in the second direction, wherein the first and second sections are connected to each other through one or more additional sections formed in the second semiconductor wafer. ### Claim 12 (depends on 11) The semiconductor die of claim 11, wherein the integrated circuits are in an active area of the semiconductor die, and wherein the set of one or more reservoirs comprise a plurality of reservoirs in one or more borders around the active area. ### Claim 13 (depends on 11) The semiconductor die of claim 11, wherein the integrated circuits are in an active area of the semiconductor die, and wherein the set of one or more reservoirs comprise a one or more reservoirs in the active area of the die. ### Claim 14 (depends on 11) The semiconductor die of claim 11, wherein a reservoir from the set of one or more reservoirs comprises a base section distal from the first major surface and a neck section more proximal to the first major surface than the base section, and wherein the base section is wider than the neck section. ### Claim 15 A semiconductor device, comprising: a signal carrier medium comprising first and second opposed major surfaces, the first surface defining a first direction parallel to the first surface, and a second direction between the first and second opposed major surfaces; and a set of one or more reservoirs formed in the signal carrier medium and open to at one of the first and second major surfaces, the set of one or more reservoirs configured to receive a flowable metal to clamp the semiconductor device to a second semiconductor device upon hardening of the flowable metal in the set of one or more reservoirs, a reservoir of the set of one or more reservoirs comprising: a first section having a first sub-section extending in the first direction, and a second sub-section extending in the second direction, and a second section having a third sub-section extending in the first direction and a fourth sub-section extending in the second direction, wherein the first and second sections are connected to each other through one or more additional sections formed in the second semiconductor wafer. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein one of the semiconductor device and second semiconductor device is a printed circuit board, and the other of the semiconductor device and second semiconductor device is a semiconductor package comprising one or more semiconductor dies. ### Claim 17 (depends on 15) The semiconductor device of claim 15, further comprising a metal within the set of one or more reservoirs, wherein the metal is configured to be a liquid or paste at a first temperature and a solid at a second temperature lower than the first temperature. ### Claim 18 (depends on 17) The semiconductor device of claim 17, wherein the metal is configured to fill at least a portion of a first reservoir of the set of one or more reservoirs in the semiconductor device, and to at least partially fill a second reservoir of the second semiconductor device, the first and second reservoirs aligned with each other, to clamp the semiconductor device to the second semiconductor device when the metal is at the second temperature. ### Claim 19 (depends on 18) The semiconductor wafer of claim 18, further comprising a third semiconductor device comprising a third set of one or more reservoirs, the metal flowing into a reservoir of the third set of one or more reservoirs to clamp the third semiconductor device to the semiconductor device and the second semiconductor device when the metal is at the second temperature.