# US 12,224,257 B2 · Semiconductor structure and manufacturing method thereof

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- Number: US 12,224,257 B2
- Document ID: US12224257B2
- Status: Granted
- Kind: B2
- Application number: 17/857,026
- Filed: 2022-07-03
- Published: 2022-10-20
- Granted: 2025-02-11
- Earliest claimed: 2019-09-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ming-Fa Chen; Hsien-Wei Chen; Jie Chen
- Web page: https://patentgrep.com/patent/US12224257B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 72/90: Bond pads, in general
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/019: {of bond pads}
- H10W 72/30: Die-attach connectors
- H10W 74/01: Manufacture or treatment
- H10W 74/114: {by a substrate and the encapsulations}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/692: Ceramics or glasses
- H10W 72/0198: {batch processes}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an integrated circuit (IC) component, an insulating layer laterally encapsulating the IC component, a redistribution structure disposed on the insulating layer and the IC component, and a warpage control portion coupling to a back side of the IC component opposite to the redistribution structure. The redistribution structure is electrically connected to the IC component. The warpage control portion includes a substrate, a patterned dielectric layer disposed between the substrate and the IC component, and a metal pattern embedded in the patterned dielectric layer and electrically isolated from the IC component.

## Claims

### Claim 1

A semiconductor structure, comprising:
an encapsulated integrated circuit (IC) component;
a redistribution structure overlying and bonded to the encapsulated IC component, wherein a bonding interface of the redistribution structure and the encapsulated IC component is substantially flat; and
a warpage control portion underlying the encapsulated IC component and comprising:
a first substrate;
a first patterned dielectric layer disposed between the first substrate and the encapsulated IC component, wherein sidewalls of the first substrate and the first patterned dielectric layer are coterminous with sidewalls of the encapsulated IC component and the redistribution structure; and
a first metal pattern laterally covered by the first patterned dielectric layer and electrically floating in the warpage control portion.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the first metal pattern of the warpage control portion is located within a distribution region overlapping an orthographic projection area of the encapsulated IC component.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a bonding layer underlying the encapsulated IC component and overlying the first patterned dielectric layer and the first metal pattern, wherein the first metal pattern is separated from the encapsulated IC component by the bonding layer.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the bonding layer is free of conductive features.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the warpage control portion further comprises:
a second dielectric layer overlying the first substrate and underlying the first patterned dielectric layer and the first metal pattern, wherein the second dielectric layer is free of conductive features.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the warpage control portion further comprises:
a second substrate;
a second patterned dielectric layer overlying the second substrate and below the first substrate, wherein sidewalls of the first substrate and the first patterned dielectric layer are coterminous with sidewalls of the second substrate and the second patterned dielectric layer;
a second metal pattern laterally covered by the second patterned dielectric layer.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, wherein the second metal pattern is electrically floating in the warpage control portion.

### Claim 8

A semiconductor structure, comprising:
an integrated circuit (IC) component comprising a first side, a second side opposite to the first side, and a sidewall connected to the first side and the second side;
an insulating layer covering the sidewall of the IC component;
a redistribution structure disposed on the insulating layer and electrically connected to the first side of the IC component; and
a warpage control portion connecting the second side of the IC component, the warpage control portion comprising a substrate and a metal pattern over the substrate, and the metal pattern being electrically floating, wherein the metal pattern is located within a distribution region overlapping an orthographic projection area of the IC component.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein the metal pattern of the warpage control portion is electrically isolated from the IC component.

### Claim 10 (depends on 8)

The semiconductor structure of claim 8, wherein outer sidewalls of the redistribution structure, the insulating layer, and the substrate, and the warpage control portion are substantially leveled with one another.

### Claim 11 (depends on 8)

The semiconductor structure of claim 8, wherein the warpage control portion further comprises a dielectric layer, top surfaces of the metal pattern and the dielectric layer are substantially leveled with each other, and bottom surfaces of the metal pattern and the dielectric layer are substantially leveled with each other.

### Claim 12

A semiconductor structure, comprising:
an integrated circuit (IC) component;
an insulating layer laterally encapsulating the IC component;
a redistribution structure disposed on the insulating layer and a front side of the IC component, the redistribution structure being electrically connected to the IC component; and
a warpage control portion coupling to a back side of the IC component, the warpage control portion comprising:
a substrate;
a patterned dielectric layer disposed between the substrate and the IC component; and
a metal pattern embedded in the patterned dielectric layer and electrically floating in the warpage control portion, wherein outer sidewalls of the redistribution structure, the insulating layer, and the warpage control portion are substantially leveled with one another.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, further comprising:
a bonding layer coupling the warpage control portion to the IC component and the insulating layer.

### Claim 14 (depends on 12)

The semiconductor structure of claim 12, wherein the warpage control portion further comprises:
an oxide layer interposed between the substrate and the patterned dielectric layer.

### Claim 15 (depends on 12)

The semiconductor structure of claim 12, wherein the metal pattern of the warpage control portion is located within a distribution region that underlies a region of the IC component.

### Claim 16 (depends on 12)

The semiconductor structure of claim 12, wherein the metal pattern of the warpage control portion comprises an alignment feature disposed in a border region surrounding a distribution region, and the distribution region directly underlies the IC component.

### Claim 17 (depends on 12)

The semiconductor structure of claim 12, wherein the metal pattern of the warpage control portion comprises:
first features distributed within a first region that underlies a region of the IC component; and
second features distributed within a second region that underlies a region of the insulating layer.

### Claim 18 (depends on 17)

The semiconductor structure of claim 17, wherein a pattern distribution density of the first features is sparser than that of the second features.

### Claim 19 (depends on 12)

The semiconductor structure of claim 12, wherein the warpage control portion further comprises:
an additional substrate;
an additional patterned dielectric layer disposed between the substrate and the additional substrate; and
an additional metal pattern embedded in the additional patterned dielectric layer.

### Claim 20 (depends on 12)

The semiconductor structure of claim 12, wherein a bonding interface of the redistribution structure and the encapsulated IC component is substantially flat.