# US 12,224,256 B2 · Wafer structure and semiconductor device

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- Number: US 12,224,256 B2
- Document ID: US12224256B2
- Status: Granted
- Kind: B2
- Application number: 17/711,370
- Filed: 2022-04-01
- Published: 2023-03-09
- Granted: 2025-02-11
- Earliest claimed: 2021-09-03
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Hyunsu Hwang; Junyun Kweon; Jumyong Park; Solji Song; Dongjoon Oh; Chungsun Lee
- Web page: https://patentgrep.com/patent/US12224256B2

## CPC

- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/42: Vias, e.g. via plugs
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 72/30: Die-attach connectors
- H10W 74/014: {using batch processing}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10W 46/101: {characterised by the type of information, e.g. logos or symbols}
- H10W 46/301: {for alignment}
- H10W 46/503: {Located in scribe lines}
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/01: {Manufacture or treatment}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/20: Configurations of stacked chips
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A wafer structure includes a semiconductor substrate that includes a chip region and a scribe lane region. A first dielectric layer is on a first surface of the semiconductor substrate, a second dielectric layer is on the first dielectric layer. A dielectric pattern is between the first dielectric layer and the second dielectric layer. A through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate, and a conductive pad is in the second dielectric layer and on the through via. The dielectric pattern includes an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad, and an alignment key pattern on the scribe lane region of the semiconductor substrate.

## Claims

### Claim 1

A wafer structure, comprising:
a semiconductor substrate that includes a chip region and a scribe lane region;
a first dielectric layer on a first surface of the semiconductor substrate;
a second dielectric layer on the first dielectric layer;
a dielectric pattern between the first dielectric layer and the second dielectric layer;
a through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate; and
a conductive pad in the second dielectric layer and on the through via,
wherein the dielectric pattern includes:
an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad; and
an alignment key pattern on the scribe lane region of the semiconductor substrate.

### Claim 2 (depends on 1)

The wafer structure of claim 1, wherein the etch stop pattern is spaced apart from the alignment key pattern.

### Claim 3 (depends on 1)

The wafer structure of claim 1, further comprising a third dielectric layer on the first dielectric layer,
wherein the third dielectric layer is between the etch stop pattern and the alignment key pattern.

### Claim 4 (depends on 3)

The wafer structure of claim 3, wherein the dielectric pattern includes a material different from a material of the first dielectric layer and different from a material of the second dielectric layer.

### Claim 5 (depends on 4)

The wafer structure of claim 4, wherein the third dielectric layer includes a same material as the material of the first dielectric layer and the material of the second dielectric layer.

### Claim 6 (depends on 1)

The wafer structure of claim 1, wherein the etch stop pattern is spaced apart from a sidewall of the through via.

### Claim 7 (depends on 6)

The wafer structure of claim 6, wherein the first dielectric layer includes an extension portion,
wherein the extension portion is between the etch stop pattern and the sidewall of the through via.

### Claim 8 (depends on 1)

The wafer structure of claim 1, wherein the second dielectric layer has:
a first top surface on the chip region; and
a second top surface on the scribe lane region,
wherein the first top surface is substantially coplanar with a top surface of the conductive pad, and
wherein the second top surface is at a level lower than a level of the top surface of the conductive pad.

### Claim 9 (depends on 8)

The wafer structure of claim 8, wherein a level difference between the top surface of the conductive pad and the second top surface of the second dielectric layer is in a range of about 0.01 μm to about 0.1 μm.

### Claim 10 (depends on 1)

The wafer structure of claim 1, wherein a width of the alignment key pattern is greater than a width of the conductive pad.

### Claim 11

A semiconductor device, comprising:
a semiconductor substrate that has a chip region and a dummy region that surrounds the chip region, in a plan view;
a first dielectric layer on a first surface of the semiconductor substrate;
a second dielectric layer on the first dielectric layer;
a dielectric pattern between the first dielectric layer and the second dielectric layer;
a through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate; and
a conductive pad in the second dielectric layer and on the through via,
wherein the dielectric pattern is spaced apart from a sidewall of the through via, and
wherein the dielectric pattern includes:
an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad; and
a dummy dielectric pattern on the dummy region of the semiconductor substrate.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein an outer sidewall of the dummy dielectric pattern is exposed by the first dielectric layer and the second dielectric layer.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the dummy dielectric pattern is a dummy alignment key pattern.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein the first dielectric layer extends between the etch stop pattern and the sidewall of the through via and is in contact with the sidewall of the through via.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein a top surface of the through via is at substantially a same level as a level of a top surface of the etch stop pattern and a level of a top surface of the dummy dielectric pattern.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, further comprising a third dielectric layer on the first dielectric layer,
wherein the dummy dielectric pattern is spaced apart from the etch stop pattern, and
wherein the third dielectric layer is between the etch stop pattern and the dummy dielectric pattern.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein
the dielectric pattern includes a material different from a material of the first dielectric layer, a material of the second dielectric layer, and a material of the third dielectric layer, and
the etch stop pattern includes a same material as a material of the dummy dielectric pattern.

### Claim 18

A wafer structure, comprising:
a semiconductor substrate that includes a chip region and a scribe lane region and having a first surface and a second surface;
a plurality of integrated circuits on the second surface at the chip region of the semiconductor substrate;
a circuit layer on the second surface of the semiconductor substrate, the circuit layer including a dielectric layer and a wiring structure, the wiring structure being in the dielectric layer and coupled to the integrated circuits;
a lower conductive pad on a bottom surface of the circuit layer and coupled to the wiring structure;
a first dielectric layer on the first surface at the chip region and the scribe lane region of the semiconductor substrate;
a second dielectric layer on the first dielectric layer;
a dielectric pattern between the first dielectric layer and the second dielectric layer;
a through via that penetrates the first dielectric layer and the chip region of the semiconductor substrate; and
a conductive pad in the second dielectric layer and on the through via, the conductive pad being coupled to the through via,
wherein the through via includes a barrier pattern and a conductive via,
wherein the barrier pattern is between the semiconductor substrate and the conductive via,
wherein the conductive pad includes a barrier pad and a metal pad on the barrier pad,
wherein the dielectric pattern includes a material different from a material of the first dielectric layer and a material different from the second dielectric layer, and
wherein the dielectric pattern includes:
an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad; and
an alignment key pattern on the scribe lane region of the semiconductor substrate.

### Claim 19 (depends on 18)

The wafer structure of claim 18, further comprising a third dielectric layer on the first dielectric layer,
wherein the third dielectric layer is between the etch stop pattern and the alignment key pattern, and
wherein the third dielectric layer overlaps the scribe lane region of the semiconductor substrate.

### Claim 20 (depends on 18)

The wafer structure of claim 18, wherein
the chip region includes a plurality of chip regions, the plurality of chip regions being arranged along rows parallel to a first direction and along columns parallel to a second direction perpendicular to the first direction,
a width in the first direction of the etch stop pattern is in a range of about 30 μm to about 180 μm, and
a width in the second direction of the etch stop pattern is in a range of about 30 μm to about 180 μm.