# US 12,224,243 B2 · Semiconductor memory device having word lines surrounded by memory layers and method of making the semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,243 B2 - Document ID: US12224243B2 - Status: Granted - Kind: B2 - Application number: 17/708,199 - Filed: 2022-03-30 - Published: 2023-10-05 - Granted: 2025-02-11 - Earliest claimed: 2022-03-30 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Meng-Han Lin; Chia-En Huang - Web page: https://patentgrep.com/patent/US12224243B2 ## CPC - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 51/30: characterised by the memory core region - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor memory device includes first and second memory units, and first and second staircase vias. The first memory unit includes two first source/bit line portions separated from each other, a first word line surrounding the first source/bit line portions, a first memory film surrounding the first word line, and a first channel region between the first memory film and the first source/bit line portions. The second memory unit is disposed over the first memory unit, and includes two second source/bit line portions separated from each other, a second word line surrounding the second source/bit line portions, a second memory film surrounding the second word line, and a second channel region between the second memory film and the second source/bit line portions. The first and second staircase vias respectively penetrate the first and second memory films, and are respectively and electrically connected to the first and second word lines. ## Claims ### Claim 1 A semiconductor memory device comprising: a first memory unit including two first source/bit line portions that extend in a first direction and that are separated from each other in a second direction perpendicular to the first direction, a first word line that extends in the second direction and that surrounds the two first source/bit line portions, a first memory film that surrounds the first word line, and a first channel region that is disposed between the two first memory film and the first source/bit line portions; a second memory unit disposed over the first memory unit in the first direction, and including two second source/bit line portions that extend in the first direction and that are separated from each other in the second direction, a second word line that extends in the second direction and that surrounds the two second source/bit line portions, a second memory film that surrounds the second word line, and a second channel region that is disposed between the second memory film and the two second source/bit line portions; a first staircase via that penetrates the first memory film and that is electrically connected to the first word line; and a second staircase via that penetrates the second memory film and that is electrically connected to the second word line. ### Claim 2 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein a height of the first staircase via is greater than a height of the second staircase via, and a width of the first staircase via is greater than a width of the second staircase via. ### Claim 3 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein: the first memory film surrounds the first channel region and the two first source/bit line portions; and the second memory film surrounds the second channel region and the two second source/bit line portions. ### Claim 4 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein: the first word line extends in the second direction away from the two first source/bit line portions, and the first staircase via penetrates a top portion of the first memory film; and the second word line extends in the second direction away from the two second source/bit line portions, and the second staircase via penetrates a top portion of the second memory film. ### Claim 5 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein: the first word line extends in the second direction beyond the second word line; and the first word line has a vertical thickness greater than a vertical thickness of the second word line. ### Claim 6 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein each of the first and second memory films has a thickness ranging from about 1 nm to about 50 nm. ### Claim 7 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein the first staircase via and the second staircase via extend in the first direction. ### Claim 8 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein the first channel region is in contact with the two first source/bit line portions. ### Claim 9 A semiconductor memory device comprising: a semiconductor structure; a plurality of dielectric segments and a plurality of conductive segments that are alternatingly stacked over the semiconductor structure in a first direction perpendicular to the semiconductor structure and that extend in a second direction perpendicular to the first direction; a plurality of channel segments that extend through the dielectric segments and the conductive segments in the first direction; a plurality of conductive lines that extend in the first direction, each of the channel segments surrounding corresponding two of the conductive lines; a plurality of memory segments, each of the memory segments surrounding the channel segments, and surrounding a respective one of the conductive segments; and a plurality of staircase vias that respectively penetrate the memory segments and that are respectively and electrically connected to the conductive segments. ### Claim 10 (depends on 9) The semiconductor memory device as claimed in claim 9, wherein widths of the staircase vias increase away from the channel segments and the conductive lines. ### Claim 11 (depends on 10) The semiconductor memory device as claimed in claim 10, wherein: lengths of the conductive segments increase toward the semiconductor structure; and heights of the staircase vias increase away from the channel segments and the conductive lines. ### Claim 12 (depends on 11) The semiconductor memory device as claimed in claim 11, wherein thicknesses of the conductive segments increase toward the semiconductor structure. ### Claim 13 (depends on 9) The semiconductor memory device as claimed in claim 9, wherein each of the memory segments has a thickness ranging from about 1 nm to about 50 nm. ### Claim 14 (depends on 9) The semiconductor memory device as claimed in claim 9, wherein the staircase vias extend in the first direction. ### Claim 15 (depends on 9) The semiconductor memory device as claimed in claim 9, wherein each of the channel segments is in contact with the corresponding two of the conductive lines. ### Claim 16 A semiconductor memory device comprising: a semiconductor structure; a plurality of dielectric segments and a plurality of conductive segments that are alternatingly stacked over the semiconductor structure in a first direction perpendicular to the semiconductor structure and that extend in a second direction perpendicular to the first direction; a plurality of channel segments that extend through the dielectric segments and the conductive segments in the first direction; a plurality of conductive lines that extend in the first direction, each of the channel segments surrounding corresponding two of the conductive lines; a plurality of isolation segments that extend in the first direction, each of the isolation segments being disposed between corresponding two of the conductive lines and being surrounded by a corresponding one of the channel segments; a plurality of memory segments, each of the memory segments surrounding the channel segments, and surrounding a respective one of the conductive segments; and a plurality of staircase vias that respectively penetrate the memory segments and that are respectively and electrically connected to the conductive segments. ### Claim 17 (depends on 16) The semiconductor memory device as claimed in claim 16, wherein a thickness of each of the conductive segments is equal to a thickness of each of the dielectric segments. ### Claim 18 (depends on 16) The semiconductor memory device as claimed in claim 16, wherein a thickness of each of the dielectric segments is equal to a total thickness of two times a thickness of each of the memory segments and a thickness of a corresponding one of the conductive segments that is surrounded by the each of the memory segments. ### Claim 19 (depends on 16) The semiconductor memory device as claimed in claim 16, wherein each of the memory segments extends a distance beyond a corresponding one of the dielectric segments above the each of the memory segments, and a width of each of the staircase vias is smaller than the distance of a corresponding one of the memory segments that the each of the staircase vias extends through. ### Claim 20 (depends on 16) The semiconductor memory device as claimed in claim 16, wherein each of the channel segments is in contact with the corresponding two of the conductive lines and a corresponding one of the isolation segments.