# US 12,224,241 B2 · Semiconductor device and manufacturing method thereof including a conductive-material etching process to further adjust a via shape

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- Number: US 12,224,241 B2
- Document ID: US12224241B2
- Status: Granted
- Kind: B2
- Application number: 17/725,300
- Filed: 2022-04-20
- Published: 2023-05-25
- Granted: 2025-02-11
- Earliest claimed: 2021-11-22
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shih-Ming Chang
- Web page: https://patentgrep.com/patent/US12224241B2

## CPC

- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0698: {Local interconnections}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/438: {Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches}
- H10W 20/46: comprising air gaps
- H10W 20/082: {the openings being tapered via holes}
- H10W 20/4421: {the principal metal being copper}
- H10W 20/4432: {the principal metal being a noble metal, e.g. gold}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In a method of manufacturing a semiconductor device, a first conductive pattern is formed in a first interlayer dielectric (ILD) layer disposed over a substrate, a second ILD layer is formed over the first conductive pattern and the first ILD layer, a via contact is formed in the second ILD layer to contact an upper surface of the first conductive pattern, a second conductive pattern is formed over the via contact wherein a part of an upper surface of the via contact is exposed from the second conductive pattern in plan view, a part of the via contact is etched by using the second conductive pattern as an etching mask, thereby forming a space between the via contact and the second ILD layer, and a third ILD layer is formed over the second ILD layer.

## Claims

### Claim 1

A method of manufacturing a semiconductor device comprising:
forming a first conductive pattern in a first interlayer dielectric (ILD) layer disposed over a substrate;
forming a second ILD layer over the first conductive pattern and the first ILD layer;
forming a via contact in the second ILD layer to contact an upper surface of the first conductive pattern;
forming a second conductive pattern over the via contact wherein a part of an upper surface of the via contact is exposed from the second conductive pattern in plan view;
etching the part of the upper surface of the via contact by using the second conductive pattern as an etching mask, thereby forming a space between the via contact and the second ILD layer; and
forming a third ILD layer over the second ILD layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
the first conductive pattern extends in a first direction, and the second conductive pattern extends in a second direction crossing the first direction, and
before etching the part of the via contact, a width of the second conductive pattern above the via contact in the first direction is smaller than a largest width of the via contact in the first direction.

### Claim 3 (depends on 2)

The method of claim 2, wherein the part of the upper surface of the via contact is exposed at a first side of the second conductive pattern and another part of the upper surface of the via contact is exposed at a second side of the second conductive pattern, which is opposite to the first side with respect to the second conductive pattern.

### Claim 4 (depends on 1)

The method of claim 1, wherein the second conductive pattern is made of a different material than the via contact.

### Claim 5 (depends on 4)

The method of claim 4, wherein the second conductive pattern is made of a same material as the first conductive pattern.

### Claim 6 (depends on 1)

The method of claim 1, wherein by the etching the part of the via contact, a part of an upper surface of the first conductive pattern is exposed.

### Claim 7 (depends on 1)

The method of claim 1, wherein after the etching the part of the via contact, an etching depth of the via contact is smaller than a height of the via contact.

### Claim 8 (depends on 7)

The method of claim 7, wherein the etching depth of the via contact is 1% to 70% of the height of the via contact.

### Claim 9 (depends on 1)

The method of claim 1, wherein the space is fully filled by the third ILD layer.

### Claim 10 (depends on 1)

The method of claim 1, wherein the space is only partially filled by the third ILD layer so that a gap remains at a side of the via contact under the third ILD layer.

### Claim 11

A method of manufacturing a semiconductor device comprising:
forming a first conductive pattern in a first interlayer dielectric (ILD) layer disposed over a substrate;
forming a second ILD layer over the first conductive pattern and the first ILD layer;
forming a via contact in the second ILD layer to contact an upper surface of the first conductive pattern;
forming a second conductive pattern over the via contact wherein a part of an upper surface of the via contact is exposed from the second conductive pattern at both sides of the second conductive pattern in plan view;
etching the part of the via contact, thereby forming spaces between the via contact and the second ILD layer; and
forming a third ILD layer over the second ILD layer, wherein:
the second conductive pattern is formed by etching using a hard mask pattern as an etching mask, and
the part of the via contact is etched by using the hard mask pattern as an etching mask.

### Claim 12 (depends on 11)

The method of claim 11, wherein:
the first conductive pattern extends in a first direction, and the second conductive pattern extends in a second direction crossing the first direction, and
before etching the part of the via contact, a width of the second conductive pattern above the via contact in the first direction is smaller than a largest width of the via contact in the first direction.

### Claim 13 (depends on 11)

The method of claim 11, wherein the hard mask pattern is made of a different material than the via contact.

### Claim 14 (depends on 11)

The method of claim 11, wherein the second conductive pattern is made of a same material as the via contact.

### Claim 15 (depends on 11)

The method of claim 11, wherein the hard mask pattern is made of a different material than the first conductive pattern.

### Claim 16 (depends on 11)

The method of claim 11, further comprising removing the hard mask pattern.

### Claim 17

A method of manufacturing a semiconductor device comprising:
forming a first conductive pattern in a first interlayer dielectric (ILD) layer disposed over a substrate;
forming a second ILD layer over the first conductive pattern and the first ILD layer;
forming a via contact in the second ILD layer to contact an upper surface of the first conductive pattern;
forming a second conductive pattern over the via contact wherein a part of an upper surface of the via contact is exposed from the second conductive pattern in plan view;
etching the second ILD layer to expose at least a part of a side face of the via contact;
etching the part of the upper surface of the via contact by using the second conductive pattern as an etching mask; and
forming a third ILD layer over the second ILD layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the second ILD layer is etched such that a part of an upper surface of the first conductive pattern is exposed.

### Claim 19 (depends on 17)

The method of claim 17, wherein the second ILD layer is etched such that no part of an upper surface of the first conductive pattern is exposed.

### Claim 20 (depends on 19)

The method of claim 19, wherein the part of the via contact is etched such that no part of an upper surface of the first conductive pattern is exposed.