# US 12,224,240 B2 · Microelectronic devices including active contacts and support contacts, and related electronic systems and methods

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- Number: US 12,224,240 B2
- Document ID: US12224240B2
- Status: Granted
- Kind: B2
- Application number: 17/396,939
- Filed: 2021-08-09
- Published: 2023-02-09
- Granted: 2025-02-11
- Earliest claimed: 2021-08-09
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: S M Istiaque Hossain; Indra V. Chary; Anilkumar Chandolu; Sidhartha Gupta; Shuangqiang Luo
- Web page: https://patentgrep.com/patent/US12224240B2

## CPC

- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/076: {in via holes or trenches}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A microelectronic device, including a stack structure including alternating conductive structures and dielectric structures is disclosed. Memory pillars extend through the stack structure. Contacts are laterally adjacent to the memory pillars and extending through the stack structure. The contacts including active contacts and support contacts. The active contacts including a liner and a conductive material. The support contacts including the liner and a dielectric material. The conductive material of the active contacts is in electrical communication with the memory pillars. Methods and electronic systems are also disclosed.

## Claims

### Claim 1

A microelectronic device, comprising:
a stack structure comprising alternating conductive structures and dielectric structures;
memory pillars extending through the stack structure; and
contacts laterally adjacent to the memory pillars and extending through the stack structure, the contacts comprising active contacts and support contacts, the active contacts comprising a liner and a conductive material and the support contacts comprising the liner and a dielectric material, the conductive material of the active contacts being in electrical communication with the memory pillars.

### Claim 2 (depends on 1)

The microelectronic device of claim 1, wherein the microelectronic device comprises a greater number of support contacts than active contacts.

### Claim 3 (depends on 1)

The microelectronic device of claim 1, further comprising a cap of dielectric materials on top of the stack structure.

### Claim 4 (depends on 1)

The microelectronic device of claim 1, wherein the conductive material of the active contacts extends through the stack structure and above the stack structure.

### Claim 5 (depends on 1)

The microelectronic device of claim 1, wherein the dielectric material of the support contacts comprises a gas.

### Claim 6 (depends on 1)

The microelectronic device of claim 1, wherein the support contacts lack the conductive material.

### Claim 7 (depends on 1)

The microelectronic device of claim 1, further comprising contacts above the memory pillars.

### Claim 8 (depends on 7)

The microelectronic device of claim 7, wherein a conductive material of the contacts above the memory pillars is a same material as the conductive material of the active contacts.

### Claim 9

A microelectronic device, comprising:
a stack structure comprising alternating conductive materials and dielectric materials;
a dielectric cap on top of the stack structure, the dielectric cap comprising two or more dielectric materials;
first contacts extending through the dielectric cap and the stack structure, the first contacts comprising a conductive material and a liner, wherein the conductive material comprises a continuous structure and lacks an interface between a portion of the conductive material adjacent to the stack structure and a portion of the conductive material adjacent to the dielectric cap; and
second contacts extending through only the stack structure, the second contacts comprising the liner and lacking a conductive material.

### Claim 10 (depends on 9)

The microelectronic device of claim 9, wherein the first contacts are laterally adjacent to the second contacts.

### Claim 11 (depends on 9)

The microelectronic device of claim 9, wherein the first contacts and the second contacts are laterally adjacent to the stack structure.

### Claim 12 (depends on 9)

The microelectronic device of claim 9, wherein the second contacts each comprise a void adjacent to the liner.

### Claim 13 (depends on 9)

The microelectronic device of claim 9, wherein the liner of the second contacts is on opposing sidewalls of the stack structure and a dielectric material is between opposing sidewalls of the liner.

### Claim 14 (depends on 9)

The microelectronic device of claim 9, wherein an upper portion of the first contacts exhibits a greater width than a lower portion of the first contacts.

### Claim 15

A method of forming a microelectronic device, the method comprising:
forming contact openings extending through a stack of alternating dielectric materials and nitride materials, the contact openings comprising first contact openings and second contact openings;
forming a slit in the stack, the slit laterally adjacent to the first contact openings and the second contact openings;
forming a first sacrificial structure in the slit;
forming a liner in the first contact openings and in the second contact openings;
forming second sacrificial structures in the first contact openings and in the second contact openings;
forming a cap over the stack and over the first and second sacrificial structures;
removing a portion of the cap over the first sacrificial structure;
removing the first sacrificial structure from the slit;
removing the nitride materials of the stack through the slit to form openings between the alternating dielectric materials of the stack;
forming a conductive material in the openings between the alternating dielectric materials of the stack to form a stack structure comprising alternating conductive structures and dielectric structures;
forming a dielectric material in the slit and over the second sacrificial structures;
removing a portion of the dielectric material and the cap to form cap openings above the second sacrificial structures in the first contact openings and above memory pillars extending through the stack structure;
removing the second sacrificial structures from the first contact openings; and
forming another conductive material in the first contact openings and in the cap openings to form contacts laterally adjacent to the memory pillars and extending through the stack structure, the contacts comprising active contacts and support contacts, the active contacts comprising the liner and the another conductive material and the support contacts comprising the liner and another dielectric material, the conductive material of the active contacts being in electrical communication with the memory pillars.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming a first sacrificial structure in the slit comprises sub-conformally forming the first sacrificial structure in the slit.

### Claim 17 (depends on 15)

The method of claim 15, wherein removing the second sacrificial structures from the first contact openings comprises removing the second sacrificial structures from the first contact openings without removing the second sacrificial structures from the second contact openings.

### Claim 18 (depends on 15)

The method of claim 15, wherein forming a conductive material in the first contact openings and in the cap openings comprises forming the contacts above the memory pillars.

### Claim 19 (depends on 15)

The method of claim 15, wherein forming a conductive material in the first contact openings and in the cap openings comprises forming the active contacts extending through the cap and the stack in a single operation.

### Claim 20 (depends on 15)

The method of claim 15, wherein forming a cap over the stack and over the first and second sacrificial structures comprises forming the cap comprising one or more of a first photoresist material, an oxide material, and a second photoresist material, and wherein forming a dielectric material in the slit and over the second sacrificial structures comprises forming the dielectric material over the cap.

### Claim 21 (depends on 15)

The method of claim 15, wherein removing a portion of the dielectric material and the cap comprises exposing the second sacrificial structures in the first contact openings and the memory pillars.

### Claim 22 (depends on 21)

The method of claim 21, wherein forming another conductive material in the first contact openings and in the cap openings to form active contacts extending through the stack comprises forming the another conductive material in the first contact openings and in the cap openings substantially simultaneously.

### Claim 23 (depends on 21)

The method of claim 21, wherein forming another conductive material in the first contact openings and in the cap openings to form active contacts extending through the stack comprises forming a portion of the another conductive material laterally adjacent to the stack and a portion of the another conductive material laterally adjacent to the cap, the portions of the another conductive material lacking an interface therebetween.

### Claim 24

An electronic system comprising:
an input device;
an output device;
a processor operatively coupled to the input device and the output device; and
a memory device operatively coupled to the processor, wherein the memory device comprises:
a stack of alternating dielectric materials and conductive materials;
a dielectric cap on top of the stack, the dielectric cap comprising one or more dielectric materials;
contact openings extending through the stack and the dielectric cap;
a conductive material and a liner in a first portion of the contact openings, the conductive material extending continuously from an upper surface of the dielectric cap to a lower surface of the stack and lacking an interface between a portion of the conductive material adjacent to the stack and a portion of the conductive material adjacent to the dielectric cap; and
the liner in a second portion of the contact openings.

### Claim 25 (depends on 24)

The electronic system of claim 24, wherein the second portion of the contact openings comprises a void adjacent to the liner.