# US 12,224,239 B2 · Internal node jumper for memory bit cells

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- Number: US 12,224,239 B2
- Document ID: US12224239B2
- Status: Granted
- Kind: B2
- Application number: 18/599,049
- Filed: 2024-03-07
- Published: 2024-06-27
- Granted: 2025-02-11
- Earliest claimed: 2021-11-11
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Smita Shridharan; Zheng Guo; Eric A. Karl; George Shchupak; Tali Kosinovsky
- Web page: https://patentgrep.com/patent/US12224239B2

## CPC

- H10W 20/43: Layouts of interconnections
- H10B 10/12: {comprising a MOSFET load element}
- H10D 84/853: {comprising FinFETs}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a fin along a first direction;
a first metal line, a second metal line and a third metal line along a second direction, the second direction orthogonal to the first direction, wherein the first metal line, the second metal line and the third metal line are within a footprint vertically over the fin; and
a first gate electrode and a second gate electrode along the second direction, the first gate electrode and the second gate electrode vertically over the fin and below the first metal line, the second metal line and the third metal line, wherein the first gate electrode and the second gate electrode but no additional gate electrodes are within the footprint of the first metal line, the second metal line and the third metal line.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein one of the first metal line, the second metal line or the third metal line is vertically over and in alignment with one of the first gate electrode or the second gate electrode.

### Claim 3 (depends on 1)

The integrated circuit structure of claim 1, further comprising:
a fourth metal line along the first direction, the fourth metal line vertically above the first gate electrode and the second gate electrode and vertically below the first metal line, the second metal line and the third metal line.

### Claim 4 (depends on 3)

The integrated circuit structure of claim 3, further comprising:
a gate contact coupling the fourth metal line to one of the first gate electrode or the second gate electrode at a location vertically over the fin.

### Claim 5 (depends on 1)

The integrated circuit structure of claim 1, wherein the first gate electrode and the second gate electrode have a first pitch, and wherein the first metal line, the second metal line and the third metal line have a second pitch, the second pitch less than the first pitch.

### Claim 6

An integrated circuit structure, comprising:
a three-dimensional semiconductor body along a first direction;
a first metal line, a second metal line and a third metal line along a second direction, the second direction orthogonal to the first direction, wherein the first metal line, the second metal line and the third metal line are within a footprint vertically over the three-dimensional semiconductor body; and
a first gate electrode and a second gate electrode along the second direction, the first gate electrode and the second gate electrode vertically over the three-dimensional semiconductor body and below the first metal line, the second metal line and the third metal line, wherein the first gate electrode and the second gate electrode but no additional gate electrodes are within the footprint of the first metal line, the second metal line and the third metal line.

### Claim 7 (depends on 6)

The integrated circuit structure of claim 6, wherein one of the first metal line, the second metal line or the third metal line is vertically over and in alignment with one of the first gate electrode or the second gate electrode.

### Claim 8 (depends on 6)

The integrated circuit structure of claim 6, further comprising:
a fourth metal line along the first direction, the fourth metal line vertically above the first gate electrode and the second gate electrode and vertically below the first metal line, the second metal line and the third metal line.

### Claim 9 (depends on 8)

The integrated circuit structure of claim 8, further comprising:
a gate contact coupling the fourth metal line to one of the first gate electrode or the second gate electrode at a location vertically over the three-dimensional semiconductor body.

### Claim 10 (depends on 6)

The integrated circuit structure of claim 6, wherein the first gate electrode and the second gate electrode have a first pitch, and wherein the first metal line, the second metal line and the third metal line have a second pitch, the second pitch less than the first pitch.

### Claim 11

A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a fin or a three-dimensional semiconductor body along a first direction;
a first metal line, a second metal line and a third metal line along a second direction, the second direction orthogonal to the first direction, wherein the first metal line, the second metal line and the third metal line are within a footprint vertically over the fin or the three-dimensional semiconductor body; and
a first gate electrode and a second gate electrode along the second direction, the first gate electrode and the second gate electrode vertically over the fin or the three-dimensional semiconductor body and below the first metal line, the second metal line and the third metal line, wherein the first gate electrode and the second gate electrode but no additional gate electrodes are within the footprint of the first metal line, the second metal line and the third metal line.

### Claim 12 (depends on 11)

The computing device of claim 11, comprising the fin.

### Claim 13 (depends on 11)

The computing device of claim 11, comprising the three-dimensional semiconductor body.

### Claim 14 (depends on 11)

The computing device of claim 11, further comprising:
a memory coupled to the board.

### Claim 15 (depends on 11)

The computing device of claim 11, further comprising:
a communication chip coupled to the board.

### Claim 16 (depends on 11)

The computing device of claim 11, further comprising:
a battery coupled to the board.

### Claim 17 (depends on 11)

The computing device of claim 11, further comprising:
a camera coupled to the board.

### Claim 18 (depends on 11)

The computing device of claim 11, further comprising:
a display coupled to the board.

### Claim 19 (depends on 11)

The computing device of claim 11, wherein the component is a packaged integrated circuit die.

### Claim 20 (depends on 11)

The computing device of claim 11, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.