# US 12,224,237 B2 · Method of manufacturing a via and a metal wiring for a semiconductor device

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- Number: US 12,224,237 B2
- Document ID: US12224237B2
- Status: Granted
- Kind: B2
- Application number: 17/488,271
- Filed: 2021-09-28
- Published: 2022-11-24
- Granted: 2025-02-11
- Earliest claimed: 2021-05-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shih-Ming Chang; Yu-Tse Lai
- Web page: https://patentgrep.com/patent/US12224237B2

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/42: Vias, e.g. via plugs
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 50/73: {using masks for insulating materials}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/0698: {Local interconnections}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In a method of manufacturing a semiconductor device, a first conductive layer is formed over a first interlayer dielectric (ILD) layer disposed over a substrate, a second ILD layer is formed over the first conductive layer, a via is formed in the second ILD layer to contact an upper surface of the first conductive layer, a hard mask pattern is formed over the second ILD layer, the second ILD layer and the first conductive layer are patterned by using the hard mask pattern as an etching mask, thereby forming patterned second ILD layers and first wiring patterns, after the patterning, the hard mask pattern is removed, and a third ILD layer is formed between the patterned second ILD layers and the first wiring patterns.

## Claims

### Claim 1

A method of manufacturing a semiconductor device comprising:
forming a first conductive layer over a first interlayer dielectric (ILD) layer disposed over a substrate;
forming a second ILD layer over the first conductive layer;
forming a via in the second ILD layer to contact an upper surface of the first conductive layer;
forming a hard mask pattern over the second ILD layer;
transferring the hard mask pattern into the second ILD layer and first conductive layer, thereby forming patterned second ILD layers and patterned first wiring patterns;
after the patterning, removing the hard mask pattern; and
forming a third ILD layer between the patterned second ILD layers and the patterned first wiring patterns.

### Claim 2 (depends on 1)

The method of claim 1, wherein the hard mask pattern is in contact with an upper surface of the via.

### Claim 3 (depends on 2)

The method of claim 2, wherein a part of the upper surface of the via is exposed from the hard mask pattern, and the via is also used as an etching mask.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first conductive layer includes one of Co, Cu or Ru.

### Claim 5 (depends on 1)

The method of claim 1, wherein the via includes one of Co, Cu or Ru.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first conductive layer and the via are made of different materials.

### Claim 7 (depends on 1)

The method of claim 1, wherein the hard mask pattern includes TiN.

### Claim 8 (depends on 1)

The method of claim 1, wherein:
the first ILD layer comprises a lower via, and
the hard mask pattern includes a pattern aligned with the lower via.

### Claim 9 (depends on 1)

The method of claim 1, wherein the via includes a body part and a cap layer disposed on the body part made of a different material than the body part.

### Claim 10 (depends on 9)

The method of claim 9, wherein the hard mask pattern is made of a same material as the cap layer.

### Claim 11

A method of manufacturing a semiconductor device comprising a lower wiring pattern, an upper wiring pattern and a pair of vias connecting the lower wiring pattern and the upper wiring pattern, the method comprising:
forming a conductive layer over a substrate;
forming a dielectric layer over the conductive layer;
forming the pair of vias in the dielectric layer;
forming a hard mask pattern over the dielectric layer;
forming an opening in the dielectric layer between the pair of vias;
extending the opening through the conductive layer to form the lower wiring pattern;
forming a second dielectric layer filling the opening; and
forming the upper wiring pattern over the pair of vias and the second dielectric layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein the lower wiring pattern is formed by:
a plasma dry etching.

### Claim 13 (depends on 12)

The method of claim 12, wherein the hard mask pattern and the pair of vias are used as a mask during the plasma dry etching.

### Claim 14 (depends on 13)

The method of claim 13, wherein the hard mask pattern is formed by using a damascene process.

### Claim 15

A method of manufacturing a semiconductor device comprising:
forming a first interlayer dielectric (ILD) layer over a substrate;
forming a first conductive layer over the first interlayer dielectric (ILD) layer;
forming a second ILD layer over the first conductive layer;
forming a first via and a second via in the second ILD layer contacting an upper surface of the first conductive layer;
forming an opening in the second ILD layer between the first via and the second via,
wherein the opening is bounded by sidewalls of the first via and the second via;
extending the opening into the first conductive layer exposing a portion of the first ILD layer, thereby patterning the first conductive layer into a first patterned conductive layer and a second patterned conductive layer; and
forming a third ILD layer between the first patterned conductive layer and the second patterned conductive layer and between the first via and the second via.

### Claim 16 (depends on 15)

The method according to claim 15, further comprising forming the third ILD layer over an uppermost surface of the second ILD layer.

### Claim 17 (depends on 16)

The method according to claim 16, further comprising planarizing uppermost surfaces of the third ILD layer and the first and second vias.

### Claim 18 (depends on 15)

The method according to claim 15, wherein the first conductive layer includes one of Co, Cu or Ru.

### Claim 19 (depends on 15)

The method according to claim 15, wherein the first via and the second via include one of Co, Cu or Ru.

### Claim 20 (depends on 15)

The method according to claim 15, wherein the first conductive layer and the first and second vias are made of different materials.