# US 12,224,233 B2 · Packaged electronic devices having dielectric substrates with thermally conductive adhesive layers

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- Number: US 12,224,233 B2
- Document ID: US12224233B2
- Status: Granted
- Kind: B2
- Application number: 17/159,925
- Filed: 2021-01-27
- Published: 2022-07-28
- Granted: 2025-02-11
- Earliest claimed: 2021-01-27
- Assignees: Wolfspeed, Inc.
- Applicants: Wolfspeed, Inc.
- Inventors: Sayan Seal; Kuldeep Saxena; Devarajan Balaraman
- Web page: https://patentgrep.com/patent/US12224233B2

## CPC

- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 40/778: {in encapsulations}
- H10W 70/479: {on or in insulating or insulated package substrates, interposers, or redistribution layers}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 72/07552: {changes in structures or sizes}
- H10W 72/527: {Multiple bond wires having different sizes}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A packaged electronic device comprises a power semiconductor die that comprises a first terminal and a second terminal, a lead frame comprising a lower side and an upper side that comprises a die pad region, a first lead and a second lead, wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame, a dielectric substrate, and a thermally conductive adhesion layer on an upper side of the dielectric substrate. The power semiconductor die is on the die pad region of the lead frame and the lead frame is on an upper side of the thermally conductive adhesion layer.

## Claims

### Claim 1

A packaged electronic device, comprising:
a power semiconductor die that comprises a first terminal and a second terminal;
a lead frame comprising a lower side and an upper side that comprises a die pad region;
a first lead and a second lead;
a dielectric substrate;
a lower metal cladding layer on a lower side of the dielectric substrate;
a first metal braze layer on an upper side of the dielectric substrate; and
a second metal braze layer is between an upper side of the lower metal cladding layer and the lower side of the dielectric substrate,
wherein the power semiconductor die is on the die pad region of the lead frame and the lead frame is on an upper side of the first metal braze layer, and
wherein the first metal braze layer is directly attached to the dielectric substrate and to the lower side of the lead frame.

### Claim 2 (depends on 1)

The packaged electronic device of claim 1, further comprising an overmold package that encapsulates an upper side and side surfaces of the power semiconductor die.

### Claim 3 (depends on 1)

The packaged electronic device of claim 1, wherein the lead frame comprises a first type of metal and the lower metal cladding layer also comprises the first type of metal.

### Claim 4 (depends on 1)

The packaged electronic device of claim 1, wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame.

### Claim 5 (depends on 4)

The packaged electronic device of claim 4, wherein the second lead is separate from the lead frame and is directly bonded to the second terminal of the power semiconductor die.

### Claim 6

A packaged electronic device, comprising:
a dielectric substrate;
a first metal cladding layer on a lower side of the dielectric substrate;
a lead frame that has an upper side that comprises a die pad region and a lower side that is on an upper side of the dielectric substrate;
a first power semiconductor die that is on the die pad region of the lead frame;
a first metal braze layer between the first metal cladding layer and the dielectric substrate; and
a second metal braze layer on the upper side of the dielectric substrate, wherein the second metal braze layer is directly attached to both the upper side of the dielectric substrate and to the lower side of the lead frame.

### Claim 7 (depends on 6)

The packaged electronic device of claim 6, further comprising an overmold encapsulation that encapsulates an upper side and side surfaces of the first power semiconductor die and at least an upper side of the dielectric substrate.

### Claim 8 (depends on 7)

The packaged electronic device of claim 7, wherein the dielectric substrate comprises a ceramic substrate.

### Claim 9 (depends on 6)

The packaged electronic device of claim 6, wherein the lead frame further comprises a first lead that is integral with and electrically connected to the die pad region, the packaged electronic device further comprising a second lead that is directly bonded to a first terminal of the first power semiconductor die.

### Claim 10 (depends on 6)

The packaged electronic device of claim 6, further comprising a second power semiconductor die that is on the lead frame and electrically connected to the first power semiconductor die.

### Claim 11 (depends on 10)

The packaged electronic device of claim 10, wherein the first and second power semiconductor die are electrically connected in parallel.

### Claim 12 (depends on 10)

The packaged electronic device of claim 10, wherein a second terminal of the first power semiconductor die is electrically connected to the first lead through the lead frame, and a first terminal of the second power semiconductor die is also electrically connected to the first lead through the lead frame.

### Claim 13

A packaged electronic device, comprising:
a dielectric substrate;
a first metal braze layer on an upper surface of the dielectric substrate;
a thermally-conductive adhesive paste;
a lead frame on the first metal braze layer;
a first metal cladding layer on a lower side of the dielectric substrate;
a second metal braze layer between the first metal cladding layer and the dielectric substrate;
a power semiconductor die that is mounted on an upper side of the lead frame;
an overmold encapsulation that surrounds an upper side and side surfaces of the power semiconductor die and at least partially surrounds sidewalls of the dielectric substrate while exposing at least a portion of the first metal cladding layer; and
a first lead and a second lead that each extend through the overmold encapsulation and that are electrically connected to the power semiconductor die,
wherein the power semiconductor die is electrically isolated from the first metal cladding layer, and
wherein the first metal braze layer is directly attached to the dielectric substrate and to a second metal cladding layer.

### Claim 14 (depends on 13)

The packaged electronic device of claim 13, wherein the dielectric substrate comprises a ceramic substrate.

### Claim 15 (depends on 13)

The packaged electronic device of claim 13, wherein the first lead is integral with the lead frame and is electrically connected to a first terminal of the power semiconductor die.

### Claim 16 (depends on 15)

The packaged electronic device of claim 15, wherein the second lead is directly bonded to a second terminal of the power semiconductor die.

### Claim 17 (depends on 13)

The packaged electronic device of claim 13, wherein a thermally-conductive adhesive paste is between the first metal braze layer and the lead frame.