# US 12,224,228 B2 · Packaged component with composite pin structure and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,228 B2 - Document ID: US12224228B2 - Status: Granted - Kind: B2 - Application number: 17/741,872 - Filed: 2022-05-11 - Published: 2023-10-12 - Granted: 2025-02-11 - Earliest claimed: 2022-04-08 - Assignees: Panjit International Inc. - Applicants: Panjit International Inc. - Inventors: Yung-Hui Wang; Chung-Hsiung Ho; Chi-Hsueh Li - Web page: https://patentgrep.com/patent/US12224228B2 ## CPC - H10W 72/50: Bond wires - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 72/075: {of bond wires} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method for manufacturing a packaged component with a composite pin structure has: dividing a substrate into a body area and a pin area, wherein a chip is arranged on the body area of the substrate and is electrically connected to conductive layers on the opposite surfaces of the substrate. The pin area is pre-defined with multiple parallel pin positions. After the electrical connection of the chip is completed in the body area, a cutting tool is used to cut along the peripheries of the body area and the pin positions to obtain a packaged component body and multiple pins. Each of the pins is integrally formed by the substrate of the packaged component body without using a conventional lead frame. ## Claims ### Claim 1 A packaged component with a composite pin structure, comprising: a substrate having a body area and a pin area, wherein the substrate comprises an insulation body and multiple conductive layers, and the body area of the substrate is formed with a chip placement opening; a chip placed in the chip placement opening; a protective layer covering the body area to form peripheral surfaces of a packaged component body; the pin area having multiple pins, extending outward from the packaged component body and electrically connected to the chip, wherein each of the multiple pins has a composite laminated structure, and the composite laminated structure includes: the insulation body integrally extending from the packaged component body; the multiple conductive layers, disposed on opposite surfaces of the insulation body of the substrate to electrically connect the chip. ### Claim 2 (depends on 1) The packaged component with a composite pin structure as claimed in claim 1, wherein two opposite surfaces of the packaged component body each respectively have the protective layer. ### Claim 3 (depends on 1) The packaged component with a composite pin structure as claimed in claim 1, wherein, the packaged component body has at least one conductive via formed inside, and the at least one conductive via is electrically connected to at least one of the multiple conductive layers. ### Claim 4 (depends on 1) The packaged component with a composite pin structure as claimed in claim 1, wherein multiple curved notches are formed on sides of each pin, and a plating layer is formed on a surface of each curved notch. ### Claim 5 (depends on 1) The packaged component with a composite pin structure as claimed in claim 1, wherein each pin includes a neck portion and a pin body; one end of the neck portion is connected to the packaged component body, and the other end of the neck portion is connected to the pin body; and a width of the neck portion is smaller than a width of the pin body. ### Claim 6 (depends on 1) The packaged component with a composite pin structure as claimed in claim 1, wherein the packaged component body is formed with multiple grooves on a surface from which the multiple pins extend outwardly, and every two of the multiple grooves are respectively adjacent to opposite sides of each pin. ### Claim 7 (depends on 1) The packaged component with a composite pin structure as claimed in claim 1, wherein each pin includes a support portion, a neck portion and a pin body extending in sequence, and one end of the support portion is connected to the packaged component body; and the support portion is wider than the pin body, and the pin body is wider than the neck portion. ### Claim 8 A method for manufacturing a packaged component with a composite pin structure, comprising: preparing a substrate and dividing the substrate into a body area and a pin area, wherein the pin area is pre-defined with multiple pin positions, the substrate includes an insulation body having opposite surfaces, and at least one conductive layer is formed on each of the opposite surfaces; forming a chip placement opening and at least one conductive via in the body area; placing a chip into the chip placement opening; electrically connecting the chip to the at least one conductive layer of the substrate and the at least one conductive via; a protective layer covering the body area to form peripheral surfaces of a packaged component body; cutting along a periphery of the body area to form the packaged component body, and along a periphery of the multiple pin positions to form multiple pins extending from the packaged component body; wherein each pin comprises the insulation body and the at least one conductive layer on the opposite surfaces of the insulation body. ### Claim 9 (depends on 8) The method as claimed in claim 8, wherein the step of electrically connecting the chip to the at least one conductive layer of the substrate includes: forming an insulating layer on a surface of the substrate, wherein the insulating layer covers the chip; forming a circuit layer on the insulating layer, wherein the circuit layer is electrically connected to the chip and extends to each pin position. ### Claim 10 (depends on 9) The method as claimed in claim 9, wherein the protective layer comprises layers that are respectively formed above the circuit layer and below the substrate in the body area. ### Claim 11 (depends on 8) The method as claimed in claim 8, wherein, when forming the chip placement opening and the at least one conductive via in the body area, multiple conductive vias are formed in the pin area and a conductive layer is formed on an inner surface of each conductive via, and the multiple conductive vias are distributed along an edge of the pin position; and in the step of forming the pins, the conductive vias are cut to form multiple curved notches on the sides of each pin. ### Claim 12 (depends on 8) The method as claimed in claim 8, wherein, in the step of forming the pins, one end of each pin adjacent to the packaged component body is partially cut to form a neck portion. ### Claim 13 (depends on 8) The method as claimed in claim 8, wherein, in the step of forming the pins, a surface of the packaged component connected to the pins is partially cut to form grooves, and every two of the multiple grooves are respectively adjacent to opposite sides of each pin. ### Claim 14 (depends on 8) The method as claimed in claim 8, wherein in the step of forming the pins, each pin includes a support portion, a neck portion and a pin body extending in sequence, and one end of the support portion is connected to the packaged component body; the support portion is wider than the pin body, and the pin body is wider than the neck portion.