# US 12,224,225 B2 · Semiconductor circuit structure with direct die heat removal structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,225 B2 - Document ID: US12224225B2 - Status: Granted - Kind: B2 - Application number: 18/674,649 - Filed: 2024-05-24 - Published: 2025-01-02 - Granted: 2025-02-11 - Earliest claimed: 2023-06-28 - Assignees: Invention and Collaboration Laboratory, Inc. - Applicants: Invention and Collaboration Laboratory, Inc. - Inventors: Chao-Chun Lu - Web page: https://patentgrep.com/patent/US12224225B2 ## CPC - H10W 40/258: {Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)} - H10D 30/62: Fin field-effect transistors [FinFET] - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 40/228: {the projecting parts being wire-shaped or pin-shaped} - H10W 70/635: {Through-vias} - H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10D 84/0151: {Manufacturing their isolation regions} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/834: {comprising FinFETs} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 90/00: Package configurations - H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2. ## Claims ### Claim 1 A semiconductor circuit structure comprising: a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction to a spare STI region, wherein the spare STI region is remote from the set of active regions; the spare STI region is connected to the first STI region, and the heat removing layer extends along the first direction to the spare STI region; wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2; and a heat removing pad within the spare STI region, wherein the heat removing layer is connected to the heat removing pad. ### Claim 2 (depends on 1) The semiconductor circuit structure of claim 1, wherein the thermal conductivity of the heat removing layer is higher than that of SiO2. ### Claim 3 (depends on 2) The semiconductor circuit structure of claim 2, wherein the heat removing layer is an electrical insulator during the operation of the semiconductor circuit structure. ### Claim 4 (depends on 2) The semiconductor circuit structure of claim 2, wherein the heat removing layer extends into one of the set of the active regions. ### Claim 5 (depends on 2) The semiconductor circuit structure of claim 2, wherein the heat removing layer includes a metal layer and a thin insulating layer, and the thin insulating layer is between the metal layer and the set of active regions. ### Claim 6 (depends on 2) The semiconductor circuit structure of claim 2, wherein the heat removing layer includes a composite material. ### Claim 7 (depends on 2) The semiconductor circuit structure of claim 2, wherein the first STI region further includes a SiO2 layer under the heat removing layer. ### Claim 8 (depends on 1) The semiconductor circuit structure of claim 1, wherein the heat removing layer is within a front end of line (FEOL) region of the semiconductor circuit structure. ### Claim 9 (depends on 1) The semiconductor circuit structure of claim 1, wherein the first STI region surrounds the set of active regions. ### Claim 10 (depends on 9) The semiconductor circuit structure of claim 9, wherein the heat removing layer is within the first STI region and positioned under the original semiconductor surface, and the heat removing layer surrounds a peripheral border of the set of active regions. ### Claim 11 (depends on 1) The semiconductor circuit structure of claim 1, wherein the spare STI region is close to a center of the semiconductor substrate, or close to an edge portion of the semiconductor substrate. ### Claim 12 (depends on 1) The semiconductor circuit structure of claim 1, further comprising a thermal via above the spare STI region and connected to the heat removing pad within the spare STI region. ### Claim 13 (depends on 12) The semiconductor circuit structure of claim 12, further comprising a heat dissipation plate above and connected to the thermal via. ### Claim 14 (depends on 12) The semiconductor circuit structure of claim 12, further comprises a plurality of insulators above the set of active regions, wherein the thermal via penetrates through the plurality of insulators and connects to the heat removing pad within the spare STI region. ### Claim 15 (depends on 14) The semiconductor circuit structure of claim 14, wherein the plurality of insulators and the thermal via are within a back end of line (BEOL) region of the semiconductor circuit structure. ### Claim 16 (depends on 1) The semiconductor circuit structure of claim 1, further comprising a through semiconductor via (TSV) extending from a backside surface of the semiconductor substrate to a bottom surface of the heat removing pad within the spare STI region, wherein the backside surface is opposite to the original semiconductor surface. ### Claim 17 (depends on 16) The semiconductor circuit structure of claim 16, further comprising a heat dissipation plate under the backside surface of the semiconductor substrate and connected to the through semiconductor via. ### Claim 18 (depends on 1) The semiconductor circuit structure of claim 1, wherein the first STI region surrounds four sidewalls of one of the set of the active regions. ### Claim 19 A semiconductor circuit structure comprising: a semiconductor substrate with an original semiconductor surface; a first set of active regions within the semiconductor substrate and extending along a first direction; a second set of active regions within the semiconductor substrate and extending along the first direction; and a first shallow trench isolation (STI) region between the first set of active regions and the second set of active regions, the first shallow trench isolation (STI) region extending along the first direction to a spare STI region which is remote from the first set of active regions and the second set of active regions; wherein the first STI region includes a heat removing layer extending along the first direction to the spare STI region, and the thermal conductivity of the heat removing layer is higher than that of SiO2; wherein the spare STI region is connected to the first STI region and includes a heat removing pad within the spare STI region, wherein the heat removing layer is connected to the heat removing pad. ### Claim 20 (depends on 19) The semiconductor circuit structure of claim 19, wherein a width of the heat removing pad is greater than a width of the heat removing layer.