# US 12,224,221 B2 · Packaging method and package structure

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- Number: US 12,224,221 B2
- Document ID: US12224221B2
- Status: Granted
- Kind: B2
- Application number: 17/863,400
- Filed: 2022-07-13
- Published: 2023-10-26
- Granted: 2025-02-11
- Earliest claimed: 2022-04-22
- Assignees: Harvatek Corporation
- Applicants: Harvatek Corporation
- Inventors: Chin-Jui Liang; Hui-Yen Huang; Ping-Lung Wang
- Web page: https://patentgrep.com/patent/US12224221B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 74/017: {Auxiliary layers for moulds, e.g. release layers or layers preventing residue}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 72/874: {On different surfaces}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/334: {Thermocompression bonding}
- H10W 90/00: Package configurations
- H10W 90/731: {of die-attach connectors}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/796: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A packaging method and a package structure are provided. The packaging method includes the following steps. Firstly, a plurality of chips are disposed on a carrying surface of a carrying board for chip redistribution. Each of the chips includes a first side connected to the carrying surface and a second side opposite to the first side, and the second side is provided with at least one chip connecting member. Next, a base structure is provided. The base structure has a bonding surface provided with a plurality of predetermined areas for bonding the chips respectively, and each of the predetermined regions has at least one electrically connecting structure formed therein. Lastly, an encapsulating material is applied to integrate the base structure, the chips, and the carrying board into a unitary structure under specific hot pressing conditions.

## Claims

### Claim 1

A packaging method, comprising:
providing a carrying board having a carrying surface;
disposing a plurality of chips on the carrying surface of the carrying board, wherein each of the chips includes a first side connected to the carrying surface and a second side opposite to the first side, and the second side is provided with at least one chip connecting member; and
providing a base structure and integrating the base structure, the chips, and the carrying board into a unitary structure under hot pressing conditions via an encapsulating material;
wherein the base structure has a bonding surface provided with a plurality of predetermined regions for bonding the chips respectively, and each of the predetermined regions has at least one electrically connecting structure formed therein;
wherein the at least one chip connecting member of each of the chips and the at least one electrically connecting structure in the corresponding one of the predetermined regions have a metal-to-metal bond formed therebetween and under the hot pressing conditions, the encapsulating material is formed into an encapsulating layer under the hot pressing conditions, and the encapsulating layer is located between the carrying board and the base structure to isolate the chips from the external environment.

### Claim 2 (depends on 1)

The packaging method according to claim 1, wherein the hot pressing conditions include a vacuum degree, a predetermined pressure, a predetermined temperature, and a predetermined time period, the vacuum degree is from 10−5 Torr to 10−1 Torr, the predetermined pressure is from 1 MPa to 100 MPa, the predetermined temperature is from 25° C. to 280° C., and the predetermined time period is from 1 second to 600 seconds.

### Claim 3 (depends on 1)

The packaging method according to claim 1, wherein the metal-to-metal bond is a copper-to-copper direct bond, a silver-to-silver direct bond, a gold-to-tin eutectic bond, a gold-to-silver eutectic bond, a palladium-to-tin eutectic bond, a palladium-to-silver eutectic bond, or a palladium-to-copper eutectic bond.

### Claim 4 (depends on 1)

The packaging method according to claim 1, further comprising: removing the carrying board and disposing a functional layer on the chips.

### Claim 5 (depends on 4)

The packaging method according to claim 4, wherein the functional layer is a heat dissipating layer.

### Claim 6 (depends on 1)

The packaging method according to claim 1, wherein in the step of disposing the chips on the carrying surface of the carrying board, each of the chips is fixed to the carrying surface of the carrying board by an adhesive material.

### Claim 7

A package structure, comprising:
a carrying board having a carrying surface;
a plurality of chips disposed on the carrying surface of the carrying board, wherein each of the chips includes a first side connected to the carrying surface and a second side opposite to the first side, and the second side is provided with at least one chip connecting member;
a base structure having a bonding surface provided with a plurality of predetermined regions for bonding the chips respectively, wherein each of the predetermined regions has at least one electrically connecting structure formed therein; and
an encapsulating layer located between the carrying board and the base structure to isolate the chips from the external environment;
wherein the at least one chip connecting member of each of the chips and the at least one electrically connecting structure in the corresponding one of the predetermined regions have a metal-to-metal bond formed therebetween, and the metal-to-metal bond and the encapsulating layer are both formed under hot pressing conditions.

### Claim 8 (depends on 7)

The package structure according to claim 7, wherein the metal-to-metal bond is a copper-to-copper direct bond, a silver-to-silver direct bond, a gold-to-tin eutectic bond, a gold-to-silver eutectic bond, a palladium-to-tin eutectic bond, a palladium-to-silver eutectic bond, or a palladium-to-copper eutectic bond.

### Claim 9 (depends on 7)

The package structure according to claim 7, wherein the second side of each of the chips is further provided with a plurality of contact pads and a redistribution structure formed on the contact pads, and the at least one chip connecting member is formed on the redistribution structure and in electrical contact with the contact pads.

### Claim 10 (depends on 7)

The package structure according to claim 7, wherein the base structure is a circuit board, a lead frame, or a package substrate.