# US 12,224,219 B2 · Package structure and circuit layer structure including dummy trace and manufacturing method therefor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,219 B2 - Document ID: US12224219B2 - Status: Granted - Kind: B2 - Application number: 17/898,299 - Filed: 2022-08-29 - Published: 2022-12-29 - Granted: 2025-02-11 - Earliest claimed: 2020-11-06 - Assignees: Advanced Semiconductor Engineering, Inc. - Applicants: Advanced Semiconductor Engineering, Inc. - Inventors: Wen-Long Lu - Web page: https://patentgrep.com/patent/US12224219B2 ## CPC - H10W 74/114: {by a substrate and the encapsulations} - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10P 72/74: {using temporarily an auxiliary support} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 74/014: {using batch processing} - H10W 74/129: {forming a chip-scale package [CSP]} - H10W 90/00: Package configurations - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads} - H10W 70/63: Vias, e.g. via plugs - H10W 70/685: comprising multiple insulating layers - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A package structure and a circuit layer structure are provided in the present disclosure. The package structure includes a wiring structure, a first electronic device, a second electronic device and at least one dummy trace. The wiring structure includes a plurality of interconnection traces. The first electronic device and the second electronic device are disposed on the wiring structure, and electrically connected to each other through the interconnection traces. The dummy trace is adjacent to the interconnection traces. A mechanical strength of the at least one dummy trace is less than a mechanical strength of one of the interconnection traces. ## Claims ### Claim 1 A package structure, comprising: a wiring structure including a plurality of interconnection traces; at least one electronic device disposed over the wiring structure, and electrically connected to the plurality of interconnection traces; and at least one testing trace adjacent to the plurality of interconnection traces, wherein the wiring structure includes a plurality of circuit layers, wherein the plurality of interconnection traces are disposed at the plurality of circuit layers, and the at least one testing trace is disposed above the plurality of interconnection traces, wherein the at least one electronic device includes two electronic devices; wherein in a top view, a high density region is located between the two electronic devices, and the at least one testing trace is located outside the high density region. ### Claim 2 (depends on 1) The package structure of claim 1, wherein in the top view, the at least one testing trace is closer to an edge of the wiring structure than the two electronic devices are. ### Claim 3 (depends on 2) The package structure of claim 2, wherein a longitudinal axis of the at least one testing trace is non-parallel with a longitudinal axis of one of the plurality of interconnection traces. ### Claim 4 (depends on 1) The package structure of claim 1, wherein in a top view, the at least one testing trace includes a neck-shape portion. ### Claim 5 (depends on 4) The package structure of claim 4, wherein in the top view, the neck-shape portion includes a segment having a consistent width. ### Claim 6 (depends on 1) The package structure of claim 1, wherein the at least one testing trace and the plurality of interconnection traces are formed of a same material. ### Claim 7 (depends on 1) The package structure of claim 1, wherein each of the plurality of circuit layers is a redistribution layer (RDL). ### Claim 8 (depends on 1) The package structure of claim 1, wherein the at least one testing trace and the plurality of interconnection traces are formed concurrently through a same manufacturing process. ### Claim 9 (depends on 1) The package structure of claim 1, wherein the at least one testing trace and the plurality of interconnection traces are disposed at a same one of the plurality of circuit layers. ### Claim 10 A circuit layer structure, comprising: a wiring structure including a plurality of interconnection traces; and at least one testing trace disposed adjacent to the plurality of interconnection traces, wherein a mechanical strength of a first portion of the at least one testing trace is greater than a mechanical strength of a second portion of the at least one testing trace, wherein in a top view, a width of the first portion of the at least one testing trace is greater than a width of the second portion of the at least one testing trace, wherein in the top view, the first portion of the at least one testing trace tapers toward the second portion of the at least one testing trace. ### Claim 11 (depends on 10) The circuit layer structure of claim 10, wherein the first portion of the at least one testing trace is located at two ends of the second portion of the at least one testing trace. ### Claim 12 (depends on 10) The circuit layer structure of claim 10, wherein in the top view, the second portion of the at least one testing trace has a consistent width. ### Claim 13 (depends on 12) The circuit layer structure of claim 12, wherein the width of the second portion of the at least one testing trace is substantially equal to a width of each of the plurality of interconnection traces. ### Claim 14 (depends on 10) The circuit layer structure of claim 10, wherein in a top view, a length of the first portion of the at least one testing trace is greater than a length of the second portion of the at least one testing trace.