# US 12,224,212 B2 · Semiconductor devices with backside air gap dielectric

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- Number: US 12,224,212 B2
- Document ID: US12224212B2
- Status: Granted
- Kind: B2
- Application number: 18/323,907
- Filed: 2023-05-25
- Published: 2023-09-21
- Granted: 2025-02-11
- Earliest claimed: 2020-05-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chun-Yuan Chen; Huan-Chieh Su; Cheng-Chi Chuang; Yu-Ming Lin; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US12224212B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6682: {the compound being a silane, e.g. disilane, methylsilane or chlorosilane}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 95/062: {involving a dielectric removal step}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/43: Layouts of interconnections
- H10W 20/46: comprising air gaps
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/427: {Power or ground buses}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain epitaxial features; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside; and a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.

## Claims

### Claim 1

A semiconductor structure having a frontside and a backside, comprising:
an isolation structure at the backside;
one or more transistors at the frontside, the one or more transistors having source/drain epitaxial features;
two metal plugs through the isolation structure and contacting two of the source/drain epitaxial features from the backside; and
a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein side portions of the dielectric liner directly contact the two metal plugs, and the side portions vary in thickness to form an over-hang profile.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein a side portion of the dielectric liner closer towards the backside is thicker than another side portion of the dielectric liner further from the backside.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein a top portion of the air gap closer to the backside is narrower than a middle portion of the air gap further from the backside.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein side portions of the dielectric liner have a thickness in a range from about 0.5 nm to 10 nm, and the space between the two metal plugs has a width in a range from about 10 nm to about 500 nm.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1,
wherein the one or more transistors further includes an active region between the two source/drain epitaxial features,
wherein the space between the two metal plugs is wider than a width of the active region in a cross-section view cut along a first direction from one of the two metal plugs to another one of the two metal plugs.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, wherein the two source/drain epitaxial features and the active region are each separated from the air gap by a bottom portion of the dielectric liner.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the bottom portion of the dielectric liner has a thickness in a range from about 0.5 nm to 10 nm in a vertical direction.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric liner partially surrounds the air gap, further comprising:
an interconnect structure over the dielectric liner and the metal plugs and at the backside, wherein the interconnect structure and the dielectric liner collectively fully surround the air gap.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric liner fully surrounds the air gap.

### Claim 11 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric liner includes a low-k dielectric material having Si, O, N, or C.

### Claim 12

A semiconductor structure, comprising:
a semiconductor feature;
an isolation structure disposed on sidewalls of the semiconductor feature;
a gate structure disposed on sidewalls and a top surface of the semiconductor feature and on a top surface of the isolation structure;
first and second source/drain features sandwiching the semiconductor feature;
first and second metal plugs through the isolation structure and contacting bottom surfaces of the first and second source/drain features, respectively; and
a dielectric liner contacting sidewalls of the isolation structure and sidewalls of the first and second metal plugs, wherein an air gap between the first and second metal plugs is partially or fully surrounded by the dielectric liner.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein a middle portion of the dielectric liner is thinner than both a topmost portion and a bottommost portion of the dielectric liner.

### Claim 14 (depends on 12)

The semiconductor structure of claim 12, wherein the dielectric liner includes a porous dielectric material.

### Claim 15 (depends on 12)

The semiconductor structure of claim 12, further comprising:
a first interconnect structure over the gate structure and the first and second source/drain features; and
a second interconnect structure under the dielectric liner and the first and second metal plugs, wherein the second interconnect structure and the dielectric liner together fully surrounds the air gap.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, wherein the second interconnect structure includes:
a metal line directly contacting one of the metal plugs; and
a dielectric layer over the dielectric liner and the air gap, and the dielectric layer is exposed in the air gap.

### Claim 17

A semiconductor structure having a frontside and a backside, comprising:
an isolation structure at the backside;
one or more transistors at the frontside, the one or more transistors having source/drain electrodes;
two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside;
a dielectric liner contacting sidewalls of the isolation structure and sidewalls of the two metal plugs; and
an interconnect structure over the dielectric liner at the backside,
wherein an air gap between the two metal plugs is sealed by the dielectric liner and the interconnect structure.

### Claim 18 (depends on 17)

The semiconductor structure of claim 17, wherein a first portion of the dielectric liner is thicker than a second portion of the dielectric liner, wherein the first portion of the dielectric liner is more towards the backside than the second portion of the dielectric liner.

### Claim 19 (depends on 17)

The semiconductor structure of claim 17, wherein a bottom portion of the dielectric liner directly lands on each of the two source/drain electrodes.

### Claim 20 (depends on 17)

The semiconductor structure of claim 17, wherein a bottom portion of the dielectric liner directly lands on an active region of the one or more transistors, and the active region is disposed between the two source/drain electrodes.