Manufacturing method of semiconductor device using gate-through implantation

A semiconductor device, comprising:

• a first drift region and a second drift region in a substrate;
• a first gate insulating film formed on the first and second drift regions;
• a first gate electrode formed on the first gate insulating film, the first gate electrode comprising a first upper portion, a second upper portion, and a center portion between the first upper portion and the second upper portion;
• a first source side spacer and a first drain side spacer respectively formed on the first gate insulating film and sidewalls of the first gate electrode;
• a first source region and a first drain region formed in the first and second drift regions, respectively, wherein the first source region and the first drain region have a higher dopant concentration than the first and second drift regions, respectively;
• a first source silicide layer and a first drain silicide layer respectively formed on the first source region and the first drain region;
• a first gate silicide layer formed on the center portion of the first gate electrode;
• a first source silicide blocking insulation layer in contact with the first gate insulating film, the first source region, the first drift region, the first source side spacer, and the first upper portion of the first gate electrode;
• a first drain silicide blocking insulation layer in contact with the first gate insulating film, the first drain region, the second drift region, the first drain side spacer, and the second upper portion of the first gate electrode;
• a device isolation region formed adjacent to the second drift region;
• a second gate electrode spaced apart from the device isolation region;
• a second gate insulating film disposed below the second gate electrode;
• a second source region formed adjacent to the second gate electrode;
• a second drain region spaced apart from the second gate electrode;
• a well region formed on the substrate;
• a body region formed in the well region and comprising a shallow body region and a deep body region, the shallow body region having a first body doping concentration and a first depth, the a deep body region having a second body doping concentration and a second depth, the second body doping concentration is greater than the first body doping concentration, the second depth which is greater than the first depth, wherein the body region surrounds the source region and is formed deeper than the device isolation region, and wherein the body region does not extend to the second drain region and has a same conductivity type as the well region;
• a third drift region surrounding the second drain region, wherein the third drift region comprises a first shallow drift portion and a first deep drift portion, the first shallow drift portion having a first drift doping concentration and a third depth, the first deep drift portion having a second drift doping concentration and a fourth depth, the second drift concentration is greater than the first drift doping concentration, the fourth depth is greater than the third depth,
• wherein the first shallow drift portion having the third depth extending from the shallow body region to a side of the first deep drift portion that is vertically aligned with a sidewall of the second gate electrode,
• wherein the first depth of the body region is greater than the third depth of the third drift region and the second depth of the body region is greater than the fourth depth of the third drift region;
• a second source side spacer and a second drain side spacer respectively formed on sidewalls of the second gate electrode;
• a second source silicide blocking insulation layer formed on the second source region, the body region, and the second source side spacer;
• a second drain silicide blocking insulation layer spaced apart from the second source silicide blocking insulation layer and formed on the second drain region, the third drift region, and the second drain side spacer;
• a second gate silicide layer formed between the second source silicide blocking insulation layer and the second drain silicide blocking insulation layer;
• and
• a first insulating layer formed on the first and second gate electrodes,
• wherein the first insulating layer is in direct contact with the first source silicide blocking insulation layer, the first drain silicide blocking insulation layer, the second source silicide blocking insulation layer, and the second drain silicide blocking insulation layer.