# US 12,224,210 B2 · Method for FinFet fabrication and structure thereof

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- Number: US 12,224,210 B2
- Document ID: US12224210B2
- Status: Granted
- Kind: B2
- Application number: 18/313,783
- Filed: 2023-05-08
- Published: 2023-09-07
- Granted: 2025-02-11
- Earliest claimed: 2018-09-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Han-Yu Lin; Yi-Ruei Jhan; Fang-Wei Lee; Tze-Chung Lin; Chao-Hsien Huang; Li-Te Lin; Pinyen Lin; Akira Mineji
- Web page: https://patentgrep.com/patent/US12224210B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10P 50/283: {by chemical means}
- H10P 95/062: {involving a dielectric removal step}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 10/0148: {comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers}
- H10W 10/021: {of air gaps}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/20: Air gaps
- H10P 30/40: into insulating materials
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a semiconductor fin protruding from the substrate, wherein the semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall;
an isolation layer disposed above the substrate, wherein the isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin;
a dielectric fin, wherein a bottom portion of the dielectric fin is embedded in the second portion of the isolation layer, and wherein a top portion of the dielectric fin includes an air pocket; and
a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin, wherein the gate structure seals a top opening of the air pocket.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the air pocket extends lengthwise in a direction generally perpendicular to a top surface of the substrate.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a bottommost portion of the air pocket is above a top surface of the isolation layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the gate structure includes a high-k gate dielectric layer, and the high-k gate dielectric layer seals the top opening of the air pocket.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a liner stacked between the semiconductor fin and the isolation layer.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the liner includes an oxynitride.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the air pocket is a first air pocket, and the first portion of the isolation layer includes a second air pocket.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the second air pocket extends lengthwise in a direction generally perpendicular to a top surface of the substrate.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein the first air pocket has a length measured in a lengthwise direction of the first air pocket that is larger than that of the second air pocket.

### Claim 10 (depends on 7)

The semiconductor device of claim 7, wherein a bottommost portion of the first air pocket is above a topmost portion of the second air pocket.

### Claim 11

A semiconductor device, comprising:
a substrate;
first, second, and third semiconductor fins extending from the substrate;
a dielectric material layer disposed between the first and second semiconductor fins and between the second and third semiconductor fins, the dielectric material layer having a first seam with an opening at a top surface of the dielectric material layer between the first and second semiconductor fins; and
a dielectric fin disposed between the second and third semiconductor fins, the dielectric fin having a second seam with an opening at a top surface of the dielectric fin.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the first seam and the second seam extending lengthwise along a same direction that is generally perpendicular to a top surface of the substrate.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the dielectric fin is partially embedded in the dielectric material layer.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein a lateral distance between the second and third semiconductor fins is at least twice of a lateral distance between the first and second semiconductor fins.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, further comprising:
a gate stack disposed on the first, second, and third semiconductor fins, wherein the gate stack caps the first and second seams.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, wherein an aspect ratio of the second seam is larger than an aspect ratio of the first seam.

### Claim 17

A semiconductor device, comprising:
a substrate;
first and second fins extending from the substrate;
an isolation structure disposed between the first and second fins;
a dielectric feature partially embedded in the isolation structure and disposed between the first and second fins, wherein a top surface of the dielectric feature is coplanar with top surfaces of the first and second fins; and
a gate stack over the dielectric feature and the first and second fins, wherein the gate stack seals a seam positioned in a top portion of the dielectric feature.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the dielectric feature includes a metal oxide.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the seam extends downwardly towards the substrate.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein a bottommost portion of the seam is above a top surface of the isolation structure.