# US 12,224,209 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 12,224,209 B2
- Document ID: US12224209B2
- Status: Granted
- Kind: B2
- Application number: 17/715,967
- Filed: 2022-04-08
- Published: 2023-10-12
- Granted: 2025-02-11
- Earliest claimed: 2022-04-08
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chia-Cheng Chao; Hsin-Chieh Huang; Yu-Wen Wang
- Web page: https://patentgrep.com/patent/US12224209B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10P 50/642: {Chemical etching}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/507: {characterised by inner spacers between adjacent channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/364: {of IGFETs}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A manufacturing method of a semiconductor device includes forming a stack of first semiconductor layers and second semiconductor layers alternatively formed on top of one another, where a topmost layer of the stack is one of the second semiconductor layers; forming a patterned mask layer on the topmost layer of the stack; forming a trench in the stack based on the patterned mask layer to form a fin structure; forming a cladding layer extending along sidewalls of the fin structure; and removing the patterned mask layer and a portion of the cladding layer by performing a two-step etching process, where the portion of the cladding layer is removed to form cladding spacers having a concave top surface with a recess depth increasing from the sidewalls of the fin structure.

## Claims

### Claim 1

A manufacturing method of a semiconductor device, comprising:
forming a stack of first semiconductor layers and second semiconductor layers alternatively formed on top of one another, wherein a topmost layer of the stack is one of the second semiconductor layers;
forming a patterned mask layer on the topmost layer of the stack;
forming a trench in the stack based on the patterned mask layer to form a fin structure;
forming a cladding layer extending along sidewalls of the fin structure; and
removing the patterned mask layer and a portion of the cladding layer by performing a two-step etching process, wherein the portion of the cladding layer is removed to form cladding spacers having a concave top surface with a recess depth increasing from the sidewalls of the fin structure.

### Claim 2 (depends on 1)

The manufacturing method of claim 1, wherein performing the two-step etching process comprises:
applying a first wet etchant in a first etching step; and
applying a second wet etchant different from the first wet etchant in a second etching step, wherein an etch rate of the first etchant for the cladding layer is higher than that of the second etchant for the cladding layer.

### Claim 3 (depends on 2)

The manufacturing method of claim 2, wherein the second wet etchant comprises a higher selectivity to the topmost layer of the stack and a lower selectivity to the cladding layer.

### Claim 4 (depends on 1)

The manufacturing method of claim 1, wherein the patterned mask layer has a first percentage of germanium, and the cladding layer has a second percentage of germanium, and the first percentage is higher than the second percentage.

### Claim 5 (depends on 1)

The manufacturing method of claim 1, wherein performing the two-step etching process comprises:
performing a first etching step by applying a first etchant to partially remove the cladding layer and the patterned mask layer, thereby causing top surfaces of the cladding layer and the patterned mask layer to have a concave cross-section; and
performing a second etching step by applying a second etchant to remove a remaining portion of the patterned mask layer and the portion of the cladding layer, wherein the topmost layer of the stack remains substantially intact.

### Claim 6 (depends on 1)

The manufacturing method of claim 1, further comprising:
filling a lower portion of the trench with an isolation structure before forming the cladding layer; and
forming a dielectric structure on the isolation structure in the trench before performing the two-step etching process.

### Claim 7 (depends on 1)

The manufacturing method of claim 1, further comprising:
replacing the first semiconductor layers of the fin structure to form a gate structure wrapping around each of the second semiconductor layers.

### Claim 8 (depends on 7)

The manufacturing method of claim 7, wherein during the replacing, the cladding spacers and the first semiconductor layers are removed in a same step.

### Claim 9

A manufacturing method of a semiconductor device, comprising:
forming a fin structure by using a patterned mask layer, wherein the fin structure comprises semiconductor channel layers and semiconductor sacrificial layers alternatively disposed on top of one another, a topmost layer of the fin structure is one of the semiconductor channel layers, and the patterned mask layer is formed on the topmost layer;
forming a cladding layer extending along sidewalls of the fin structure;
performing a first etching process by a first etchant to partially removing the cladding layer and the patterned mask layer; and
performing a second etching process by a second etchant to accessibly expose the topmost layer of the fin structure with cladding spacers extending along the sidewalls of the fin structure, wherein an etch rate of the first etchant for the cladding layer is greater than that of the second etchant for the cladding layer.

### Claim 10 (depends on 9)

The manufacturing method of claim 9, wherein the patterned mask layer contains silicon germanium with a first percentage of germanium, and the cladding layer contains silicon germanium with a second percentage of germanium which is less than the first percentage.

### Claim 11 (depends on 10)

The manufacturing method of claim 10, wherein when performing the first etching process, the patterned mask layer is removed faster than the cladding layer, thereby causing a top surface of the cladding layer to be higher than a top surface of the patterned mask layer.

### Claim 12 (depends on 9)

The manufacturing method of claim 9, wherein after the first etching process, a portion of the patterned mask layer is remained on the topmost layer of the fin structure.

### Claim 13 (depends on 12)

The manufacturing method of claim 12, wherein when performing the second etching process, the portion of the patterned mask layer is removed together with a portion of the cladding layer to form the cladding spacers having concave top surfaces.

### Claim 14 (depends on 9)

The manufacturing method of claim 9, wherein the etch rate of the second etchant for the cladding layer is greater than an etch rate of the second etchant for the topmost layer of the fin structure.

### Claim 15 (depends on 9)

The manufacturing method of claim 9, further comprising:
forming isolation structures along sidewalls of a semiconductor substrate on which the fin structure is formed, before forming the cladding layer;
forming dielectric structures on the isolation structures to be in contact with the cladding layer before performing the first etching process; and
replacing the semiconductor sacrificial layers of the fin structure to form a gate structure wrapping around each of the semiconductor channel layers, wherein during the replacing, the cladding spacers are removed together with the semiconductor sacrificial layers.

### Claim 16

A manufacturing method of a semiconductor device, comprising:
forming a fin structure on a semiconductor substrate by a patterned mask layer, wherein the fin structure comprises semiconductor channel layers and semiconductor sacrificial layers alternately stacked;
forming isolation structures along sidewalls of the semiconductor substrate;
forming a cladding layer on the isolation structures and along sidewalls of the fin structure;
forming dielectric structures on the isolation structures, wherein the dielectric structures are in contact with the cladding layer;
removing a portion of the cladding layer and the patterned mask layer to accessibly expose a topmost one of the semiconductor channel layers of the fin structure, wherein the portion of the cladding layer is removed to form cladding spacers with concave top surfaces; and
replacing the semiconductor sacrificial layers of the fin structure to form a gate structure wrapping around each of the semiconductor channel layers.

### Claim 17 (depends on 16)

The manufacturing method of claim 16, wherein removing the portion of the cladding layer and the patterned mask layer comprises:
applying a first wet etchant over the cladding layer and the patterned mask layer to form a concave top surface of the cladding layer and the patterned mask layer; and
applying a second wet etchant over remaining portion of the patterned mask layer and the cladding layer to completely remove the patterned mask layer and form the cladding spacers.

### Claim 18 (depends on 17)

The manufacturing method of claim 17, wherein the patterned mask layer contains silicon germanium with a first percentage of germanium, and the cladding layer contains silicon germanium with a second percentage of germanium which is less than the first percentage.

### Claim 19 (depends on 16)

The manufacturing method of claim 16, wherein during replacing the semiconductor sacrificial layers, the cladding spacers are removed together with the semiconductor sacrificial layers.

### Claim 20 (depends on 16)

The manufacturing method of claim 16, further comprising:
forming a dummy gate structure over the fin structure after the removing;
forming source/drain epitaxial structures coupled to the fin structure; and
removing the dummy gate structure before the replacing.