# US 12,224,206 B2 · Conductive structure, semiconductor structure and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,206 B2 - Document ID: US12224206B2 - Status: Granted - Kind: B2 - Application number: 17/456,631 - Filed: 2021-11-26 - Published: 2022-04-14 - Granted: 2025-02-11 - Earliest claimed: 2020-10-13 - Assignees: Changxin Memory Technologies, Inc. - Applicants: Changxin Memory Technologies, Inc. - Inventors: Ping-Heng Wu - Web page: https://patentgrep.com/patent/US12224206B2 ## CPC - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/01: {Manufacture or treatment} - H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes} - H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates} - H10W 20/0245: {comprising use of blind vias during the manufacture} - H10W 20/0261: {characterised by the filling method or the material of the conductive fill} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/2125: {Top-view shapes} - H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers} - H10W 20/216: {characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes} - H10W 20/43: Layouts of interconnections - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 90/00: Package configurations - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A conductive structure includes: a conductive pillar and at least one embedded block arranged in the conductive pillar, a coefficient of thermal expansion of the embedded block being less than that of the conductive pillar. When the conductive pillar is heated and expanded, an extrusion effect of the conductive pillar on a structure adjacent to the conductive pillar can be reduced, thereby improving the performance of the semiconductor structure. ## Claims ### Claim 1 A semiconductor structure, comprising: a base comprising a substrate, a first dielectric layer on the substrate, and a second dielectric layer on one side of the first dielectric layer away from the substrate; an electrical connection layer, the electrical connection layer being located in the second dielectric layer; and a conductive structure being located in the base, wherein the conductive structure comprises: a conductive pillar being passed through the substrate and the first dielectric layer and being electrically connected to the electrical connection layer; and at least one embedded block being located in the substrate and in the first dielectric layer, wherein the at least one embedded block is provided at one end of the conductive pillar facing the electrical connection layer and is in contact with the conductive pillar; wherein a coefficient of thermal expansion of the at least one embedded block is less than that of the conductive pillar; and a distance between the at least one embedded block and the electrical connection layer is within a preset range along a direction perpendicular to the surface of the substrate, and the preset range is 5-50 nm. ### Claim 2 (depends on 1) The semiconductor structure according to claim 1, wherein the at least one embedded block is made of a silicon-containing material or a metal material. ### Claim 3 (depends on 1) The semiconductor structure according to claim 1, wherein the at least one embedded block comprises: at least one first embedded block, and a central axis of the first embedded block coincides with that of the conductive pillar. ### Claim 4 (depends on 3) The semiconductor structure according to claim 3, wherein the at least one embedded block further comprises: a plurality of second embedded blocks spaced around the first embedded block. ### Claim 5 (depends on 1) The semiconductor structure according to claim 1, wherein the at least one embedded block encloses an annular structure. ### Claim 6 (depends on 5) The semiconductor structure according to claim 5, wherein the at least one embedded block further comprises: a third embedded block, and a central axis of the third embedded block coincides with that of the conductive pillar. ### Claim 7 (depends on 1) The semiconductor structure according to claim 1, the at least one embedded block comprises: a plurality of fin-shaped structures, some of which extend beyond the conductive pillar. ### Claim 8 A semiconductor structure manufacturing method, comprising: providing a substrate, and forming a first dielectric layer on the substrate; etching the substrate and the first dielectric layer to form at least one first through hole; filling the first through hole to form an embedded block; forming a second dielectric layer on one side of the first dielectric layer away from the substrate, and forming an electrical connection layer in the second dielectric layer, wherein the substrate, the first dielectric layer and the second dielectric layer are formed as a base; etching the substrate and the first dielectric layer until the electrical connection layer is exposed to form at least one second through hole, at least one embedded block being located in the second through hole; and filling the second through hole to form a conductive pillar, a coefficient of thermal expansion of the embedded block being less than that of the conductive pillar. ### Claim 9 (depends on 8) The semiconductor structure manufacturing method according to claim 8, wherein the electrical connection layer is electrically connected to the conductive pillar; and the at least one embedded block is formed at one end of the conductive pillar facing the electrical connection layer, wherein a distance between the embedded block and the electrical connection layer is within a preset range along a direction perpendicular to the surface of the substrate and the preset range is 5-50 nm. ### Claim 10 (depends on 8) The semiconductor structure manufacturing method according to claim 8, wherein the electrical connection layer is electrically connected to the conductive pillar; and the at least one embedded block is formed at one end of the conductive pillar facing the electrical connection layer; wherein the embedded block is in contact with the electrical connection layer.