# US 12,224,205 B2 · Semiconductor memory device and manufacturing method thereof

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- Number: US 12,224,205 B2
- Document ID: US12224205B2
- Status: Granted
- Kind: B2
- Application number: 17/647,773
- Filed: 2022-01-12
- Published: 2022-09-29
- Granted: 2025-02-11
- Earliest claimed: 2021-03-25
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Jingwen Lu
- Web page: https://patentgrep.com/patent/US12224205B2

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/098: {by filling between adjacent conductive parts}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/31: {having a storage electrode stacked over the transistor}
- H10B 12/482: {Bit lines}
- H10W 20/076: {in via holes or trenches}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10B 12/315: {with the capacitor higher than a bit line}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The present disclosure provides a semiconductor memory device and a manufacturing method thereof. The manufacturing method includes: providing a substrate having a plurality of active areas; forming a plurality of bit line structures on the substrate, where the plurality of bit line structures are sequentially provided at intervals along a first direction; forming a dielectric layer on the substrate; etching the dielectric layer, to form a plurality of contact holes and a plurality of isolation structures, where each contact hole is between the adjacent bit line structures, the plurality of contact holes and the plurality of isolation structures are alternately provided along a second direction, the first direction is not parallel to the second direction; and forming an isolation layer on a side wall of each bit line structure and a side wall of each isolation structure.

## Claims

### Claim 1

A method of manufacturing a semiconductor memory device, comprising:
providing a substrate having a plurality of active areas;
forming a plurality of bit line structures on the substrate, wherein the plurality of bit line structures are sequentially provided at intervals along a first direction;
forming a dielectric layer on the substrate, wherein the dielectric layer fills up at least a gap between adjacent bit line structures;
etching the dielectric layer, to form a plurality of contact holes and a plurality of isolation structures, wherein each contact hole is between the adjacent bit line structures, the plurality of contact holes and the plurality of isolation structures are alternately provided along a second direction, the first direction is not parallel to the second direction, and a bottom of the contact hole exposes the active area;
forming an isolation layer on a side wall of each bit line structure and a side wall of each isolation structure; and
forming the isolation layer on a top of each bit line structure and a top of each isolation structure.

### Claim 2 (depends on 1)

The method of manufacturing a semiconductor memory device according to claim 1, wherein
the step of forming an isolation layer on a side wall of each bit line structure and a side wall of each isolation structure comprises:
forming a first isolation layer on the side wall of each bit line structure and the side wall of each isolation structure; and
forming a second isolation layer on a surface of the first isolation layer, wherein
a material of the first isolation layer is different from a material of the second isolation layer.

### Claim 3 (depends on 2)

The method of manufacturing a semiconductor memory device according to claim 2, wherein
the material of the first isolation layer comprises silicon nitride, and the material of the second isolation layer comprises silicon oxide.

### Claim 4 (depends on 2)

The method of manufacturing a semiconductor memory device according to claim 2, wherein
the step of forming an isolation layer on a side wall of each bit line structure and a side wall of each isolation structure further comprises:
forming a third isolation layer on the second isolation layer, wherein
the material of the first isolation layer is the same as a material of the third isolation layer.

### Claim 5 (depends on 4)

The method of manufacturing a semiconductor memory device according to claim 4, wherein
both the material of the first isolation layer and the material of the third isolation layer comprise silicon nitride, and the material of the second isolation layer comprises silicon oxide.

### Claim 6 (depends on 1)

The method of manufacturing a semiconductor memory device according to claim 1, wherein
the step of forming a plurality of bit line structures on the substrate comprises:
forming a laminated structure on a surface of the substrate;
forming a patterned mask on a surface of the laminated structure; and
etching the laminated structure by using the patterned mask as a mask.

### Claim 7 (depends on 6)

The method of manufacturing a semiconductor memory device according to claim 6, wherein
the step of forming a laminated structure on a surface of the substrate comprises:
forming a first conductive layer on the substrate;
forming a second conductive layer on the first conductive layer; and
forming a cover layer on the second conductive layer, wherein a material of the cover layer comprises silicon oxide.

### Claim 8 (depends on 7)

The method of manufacturing a semiconductor memory device according to claim 7, wherein
after the forming a second conductive layer on the first conductive layer, and before the forming a cover layer on the second conductive layer, the method of manufacturing a semiconductor memory device further comprises:
forming an intermediate layer on the second conductive layer, wherein a material of the intermediate layer comprises silicon nitride.

### Claim 9 (depends on 7)

The method of manufacturing a semiconductor memory device according to claim 7, wherein
a material of the first conductive layer comprises TiN.

### Claim 10 (depends on 1)

The method of manufacturing a semiconductor memory device according to claim 1, wherein
after the forming a plurality of bit line structures, the method of manufacturing a semiconductor memory device further comprises:
performing a step of pre-cleaning each bit line structure.

### Claim 11

A semiconductor memory device, comprising:
a substrate having a plurality of active areas;
a plurality of bit line structures, sequentially provided at intervals on the substrate along a first direction;
a plurality of isolation structures, sequentially provided at intervals on the substrate along a second direction, wherein each isolation structure is located between adjacent bit line structures, every two adjacent bit line structures and every two adjacent isolation structures define one contact hole, a bottom of the contact hole exposes the active area, and the first direction is not parallel to the second direction; and
an isolation layer, formed on a side wall of each bit line structure and a side wall of each isolation structure;
wherein the isolation layer is further formed on a top of each bit line structure and a top of each isolation structure.

### Claim 12 (depends on 11)

The semiconductor memory device according to claim 11, wherein
the isolation layer comprises a first isolation layer and a second isolation layer, the first isolation layer is formed on the side wall of each bit line structure and the side wall of each isolation structure, and the second isolation layer is formed on a surface of the first isolation layer; and
a material of the first isolation layer is different from a material of the second isolation layer.

### Claim 13 (depends on 12)

The semiconductor memory device according to claim 12, wherein
the material of the first isolation layer comprises silicon nitride, and the material of the second isolation layer comprises silicon oxide.

### Claim 14 (depends on 12)

The semiconductor memory device according to claim 12, wherein
the isolation layer further comprises a third isolation layer, and the third isolation layer is formed on a surface of the second isolation layer; and
the material of the first isolation layer is the same as a material of the third isolation layer.

### Claim 15 (depends on 14)

The semiconductor memory device according to claim 14, wherein
both the material of the first isolation layer and the material of the third isolation layer comprise silicon nitride, and the material of the second isolation layer comprises silicon oxide.

### Claim 16 (depends on 11)

The semiconductor memory device according to claim 11, wherein
each bit line structure comprises a first conductive layer, a second conductive layer, and a cover layer, the first conductive layer is provided on the substrate, the second conductive layer is provided on a surface of the first conductive layer, and the cover layer is provided on a surface of the second conductive layer; and
a material of the cover layer comprises silicon oxide.

### Claim 17 (depends on 16)

The semiconductor memory device according to claim 16, wherein
each bit line structure further comprises an intermediate layer, the intermediate layer is provided between the second conductive layer and the cover layer, and a material of the intermediate layer comprises silicon nitride.

### Claim 18 (depends on 16)

The semiconductor memory device according to claim 16, wherein
a material of the first conductive layer comprises TiN.