# US 12,224,203 B2 · Air gap spacer formation for nano-scale semiconductor devices

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- Number: US 12,224,203 B2
- Document ID: US12224203B2
- Status: Granted
- Kind: B2
- Application number: 18/132,333
- Filed: 2023-04-07
- Published: 2024-03-07
- Granted: 2025-02-11
- Earliest claimed: 2016-08-09
- Assignees: Adeia Semiconductor Solutions LLC
- Applicants: Adeia Semiconductor Solutions LLC
- Inventors: Kangguo Cheng; Thomas J. Haigh; Juntao Li; Eric G. Liniger; Sanjay C. Mehta; Son V. Nguyen; Chanro Park; Tenko Yamashita
- Web page: https://patentgrep.com/patent/US12224203B2

## CPC

- H10W 20/46: comprising air gaps
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 64/679: {comprising air gaps}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6682: {the compound being a silane, e.g. disilane, methylsilane or chlorosilane}
- H10P 14/6905: {being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H}
- H10P 14/6922: {the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10W 20/039: {also covering sidewalls of the conductive structures}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/076: {in via holes or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/43: Layouts of interconnections
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/48: Insulating materials thereof
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a gate structure and a source/drain contact disposed adjacent to each other on a substrate;
an air gap disposed between the gate structure and the source/drain contact; and
a dielectric material disposed over the gate structure and over the air gap;
a conformal insulating liner layer comprising: (i) a first portion disposed below the air gap; (ii) a second portion disposed between the gate structure and the air gap; and (iii) a third portion disposed between the source/drain contact and the air gap, wherein:
an upper portion of the air gap is disposed above a top surface of the gate structure and below a top surface of the source/drain contact; and
a lower portion of the air gap is disposed below a bottom surface of the source/drain contact.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device further comprises an epitaxial source/drain region, and wherein:
the source/drain contact and the epitaxial source/drain region are in contact; and
the air gap extends above and below a top surface of the epitaxial source/drain region.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein a portion of the air gap is between the epitaxial source/drain region and the gate structure.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the conformal insulating liner layer comprises Si and N.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the conformal insulating liner layer comprises a plurality of layers comprising Si and N of about 0.1 to 0.2 nm in thickness.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the conformal insulating liner layer is about 1-3 nm thick.

### Claim 7 (depends on 4)

The semiconductor device of claim 4, wherein the conformal insulating liner layer is about 1-3 nm thick.

### Claim 8 (depends on 5)

The semiconductor device of claim 5, wherein the conformal insulating liner layer is about 1-3 nm thick.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the conformal insulating liner layer is about 1 nm thick.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the conformal insulating liner layer is about 1.5 nm thick.

### Claim 11 (depends on 4)

The semiconductor device of claim 4, wherein the conformal insulating liner layer is about 1 nm thick.

### Claim 12 (depends on 4)

The semiconductor device of claim 4, wherein the conformal insulating liner layer is about 1.5 nm thick.

### Claim 13 (depends on 5)

The semiconductor device of claim 5, wherein the conformal insulating liner layer is about 1 nm thick.

### Claim 14 (depends on 5)

The semiconductor device of claim 5, wherein the conformal insulating liner layer is about 1.5 nm thick.

### Claim 15 (depends on 1)

The semiconductor device of claim 1, wherein the conformal insulating liner layer comprises a plurality of conformal dielectric layers.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the conformal insulating liner layer is about 0.5 nm-5 nm thick.

### Claim 17 (depends on 1)

The semiconductor device of claim 1, wherein the source/drain contact comprises a conformal liner layer comprising Ta adjacent to the conformal insulating liner layer.

### Claim 18 (depends on 1)

The semiconductor device of claim 1, wherein a top surface of the dielectric material and a top surface of the source/drain contact are substantially coplanar.

### Claim 19 (depends on 1)

The semiconductor device of claim 1, wherein a portion of the dielectric material is disposed between the gate structure and the source/drain contact.

### Claim 20 (depends on 1)

The semiconductor device of claim 1, wherein a semiconductor fin comprising an epitaxial source/drain region is formed on the substrate and the source/drain contact is formed on the epitaxial source/drain region.